| Name | Version | Summary | date |
| tsfpga |
12.3.1 |
A flexible and scalable development platform for modern FPGA projects |
2024-03-08 09:33:37 |
| slvcodec |
0.4.18 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2024-02-27 18:25:50 |
| wal-lang |
0.8.0 |
Wal - Wavefile Analysis Language |
2024-01-29 17:06:21 |
| pyVHDLModel |
0.28.0 |
An abstract VHDL language model. |
2024-01-21 01:30:57 |
| hdlConvertor-binary |
2.3 |
VHDL and System Verilog parser written in c++ |
2024-01-06 00:37:35 |
| mio-cli |
1.3.6 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2023-12-21 01:53:28 |
| edalize |
0.5.4 |
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface |
2023-12-11 11:49:52 |
| ipxact2systemverilog |
1.0.23 |
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description |
2023-11-26 10:38:15 |
| hdlConvertorAst |
1.2 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2023-10-23 13:53:41 |
| crcgen |
2.6 |
CRC algorithm HDL code generator (VHDL, Verilog, MyHDL) |
2023-10-13 20:56:15 |
| xeda |
0.2.5 |
Cross EDA Abstraction and Automation |
2023-07-26 17:38:36 |
| dovado-rtl |
0.10.11 |
RTL Design Space Exploration on top of Vivado |
2023-04-28 08:23:25 |
| fusesoc |
2.2.1 |
FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code. |
2023-04-24 13:27:02 |