| Name | Version | Summary | date |
| liteiclink |
2023.12 |
Small footprint and configurable Inter-Chip communication cores |
2024-04-18 20:33:04 |
| chisel4ml |
0.3.0 |
A Chisel based hardware generation library for highly quantized neural networks. |
2024-03-16 15:27:56 |
| tsfpga |
12.3.1 |
A flexible and scalable development platform for modern FPGA projects |
2024-03-08 09:33:37 |
| pf-dev-tools |
1.3.0 |
A collection of tools for Project Freedom projects |
2024-03-01 11:52:57 |
| slvcodec |
0.4.18 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2024-02-27 18:25:50 |
| magia-flow |
0.1.0 |
Design flow integration and automation with Magia |
2024-02-26 21:27:04 |
| anyv-registers |
0.1.0 |
A template-based hardware register bank generator |
2024-02-25 13:44:24 |
| magia-hdl |
0.5.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-02-20 20:35:45 |
| litexcnc |
1.2.4 |
Generic CNC firmware and driver for FPGA cards which are supported by LiteX |
2024-02-18 21:30:19 |
| magia-ip |
0.0.1 |
IP libraries designed with Magia |
2024-02-18 21:21:15 |
| smartmca |
0.0.4 |
Smart MCA for DT5771 Python Library |
2024-02-12 14:24:18 |
| fxpmath |
0.4.9 |
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility. |
2024-02-08 01:34:31 |
| myhdl |
0.11.45 |
Python as a Hardware Description Language |
2024-02-04 17:47:16 |
| wal-lang |
0.8.0 |
Wal - Wavefile Analysis Language |
2024-01-29 17:06:21 |
| rapidwright |
2023.2.1 |
Xilinx RapidWright Framework Wrapped for Python. |
2024-01-11 00:22:43 |
| syn-magia |
0.3.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-01-06 20:57:03 |
| desyrdl |
1.3.0 |
DesyRDL - Tool for address space and register generation |
2024-01-04 09:37:54 |
| litex |
2023.12 |
Python SoC/Core builder for building FPGA based systems. |
2023-12-28 20:49:13 |
| mio-cli |
1.3.6 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2023-12-21 01:53:28 |
| edalize |
0.5.4 |
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface |
2023-12-11 11:49:52 |