| Name | Version | Summary | date |
| syn-magia |
0.3.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-01-06 20:57:03 |
| sverilogpy |
0.0.0a2 |
A python System Verilog Parser and AST |
2024-01-03 16:47:25 |
| cocotbext-ahb |
0.2.6 |
CocotbExt AHB Bus VIP |
2023-12-25 20:46:58 |
| mio-cli |
1.3.6 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2023-12-21 01:53:28 |
| pyucis |
0.1.3.7162246580 |
PyUCIS provides a Python API for manipulating UCIS coverage data. |
2023-12-11 02:43:32 |
| ipxact2systemverilog |
1.0.23 |
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description |
2023-11-26 10:38:15 |
| zuspec |
0.0.1.6885112054 |
Co-specification of hardware, software, design, and test behavior |
2023-11-16 01:40:00 |
| zuspec-dataclasses |
0.0.1.6741044156 |
Front-end for capturing Action Relation Level models using dataclasses |
2023-11-03 03:50:05 |
| peakrdl |
1.1.0 |
Command-line tool for control/status register automation and code generation. |
2023-10-26 04:34:44 |
| hdlConvertorAst |
1.2 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2023-10-23 13:53:41 |
| zuspec-be-sw |
0.0.1.6503696132 |
Backend library to generate software output |
2023-10-13 03:38:09 |
| pySVModel |
0.4.1 |
An abstract SystemVerilog language model (incl. Verilog). |
2023-08-15 22:19:34 |
| ipsocgen |
0.1.39 |
Generic SoC builder in HDL |
2023-06-24 22:45:09 |
| uvm-python |
0.3.0 |
uvm-python UVM implementation in Python on top of cocotb |
2023-03-29 17:07:48 |
| libarl |
0.0.1.3625797450 |
Core ARL model evaluator library |
2022-12-06 02:24:00 |
| libvsc |
0.0.1.3615208868 |
Core Verification Stimulus and Coverage library |
2022-12-04 21:50:55 |