| Name | Version | Summary | date |
| pyVHDLModel |
0.30.0 |
An abstract VHDL language model. |
2025-02-12 20:00:55 |
| slvcodec |
0.4.20 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2025-01-30 03:04:09 |
| polyphony |
0.4.0 |
Python based High Level Synthesis compiler |
2025-01-29 10:02:37 |
| bust |
0.14.1 |
Utility for simply creating and modifying VHDL bus slave modules |
2024-12-11 08:10:06 |
| edalize |
0.6.0 |
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface |
2024-11-13 20:05:24 |
| fusesoc |
2.4 |
Award-winnning package manager and build abstraction tool for HDL code |
2024-10-02 17:49:41 |
| hdlConvertor-binary |
2.3 |
VHDL and System Verilog parser written in c++ |
2024-01-06 00:37:35 |
| ipxact2systemverilog |
1.0.23 |
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description |
2023-11-26 10:38:15 |
| hdlConvertorAst |
1.2 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2023-10-23 13:53:41 |
| crcgen |
2.6 |
CRC algorithm HDL code generator (VHDL, Verilog, MyHDL) |
2023-10-13 20:56:15 |
| xeda |
0.2.5 |
Cross EDA Abstraction and Automation |
2023-07-26 17:38:36 |
| dovado-rtl |
0.10.11 |
RTL Design Space Exploration on top of Vivado |
2023-04-28 08:23:25 |