| Name | Version | Summary | date |
| fsva |
0.0.7 |
fsva (FuseSoc Verification Automation) |
2021-01-15 12:02:44 |
| axilent |
0.1.8 |
Tools for describing a sequence of Axi4Lite commands. |
2021-01-14 17:43:30 |
| slvcodec |
0.4.10 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2021-01-14 17:39:17 |
| dovado-rtl |
0.4.2 |
CLI tool for RTL Design Space Exploration on top of Vivado |
2021-01-06 20:38:12 |
| vlsim |
0.0.1.20201228.1 |
vlsim is a wrapper around Verilator that adds in a simple C++ front-end for clock generation and trace control |
2020-12-28 18:34:10 |
| ivpm |
0.0.1.20201221.1 |
IVPM (IP and Verification Package Manager) is a project-internal package manager. |
2020-12-21 02:46:49 |
| risktools |
0.1.0 |
Python implementation of the R package RTL |
2020-12-05 22:01:34 |
| pyucis |
0.0.3.20201115.1 |
PyUCIS provides a Python API for manipulating UCIS coverage data. |
2020-11-15 19:03:13 |
| pyucis-viewer |
0.0.3.20200920.2 |
PyUCIS Viewer QT5-based viewer for UCIS data. |
2020-09-20 02:26:00 |
| scratchip |
0.2.2 |
ScratChip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier. |
2020-07-22 01:57:47 |
| HdlLib |
0.1.1 |
VHDL source management : parse, organize, assemble, generate testbenches |
2017-07-10 14:41:42 |