PyDigger - unearthing stuff about Python


NameVersionSummarydate
slvcodec 0.4.17 Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. 2021-07-21 22:43:34
zarnevis 0.0.1 Zarnevis, a tool for writing RTL text in computer vision projects 2021-07-20 21:51:56
dovado-rtl 0.7.12 CLI tool for RTL Design Space Exploration on top of Vivado 2021-07-12 10:44:13
ivpm 1.0.0 IVPM (IP and Verification Package Manager) is a project-internal package manager. 2021-06-30 01:08:52
thdl 0.0.6 thdl 2021-05-18 12:59:44
edalize 0.2.5 Edalize is a library for interfacing EDA tools, primarily for FPGA development 2021-05-12 14:40:06
pyucis 0.0.4.20210502.1 PyUCIS provides a Python API for manipulating UCIS coverage data. 2021-05-02 16:57:02
knitkit 0.1 Knit Kit is a framework that can help to build project easier. 2021-04-24 13:03:14
uvm-python 0.2.0 uvm-python UVM implementation in Python on top of cocotb 2021-03-27 14:33:11
sandpiper-saas 0.9.2 Sandpiper SaaS 2021-03-19 15:00:43
fusesoc 1.12.0 FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code. 2021-02-25 21:38:30
pyucis-viewer 0.0.3.20210221.1 PyUCIS Viewer QT5-based viewer for UCIS data. 2021-02-21 23:59:03
vlsim 0.0.1.20210204.1 vlsim is a wrapper around Verilator that adds in a simple C++ front-end for clock generation and trace control 2021-02-04 01:54:21
fsva 0.0.8 fsva (FuseSoc Verification Automation) 2021-01-21 15:43:48
axilent 0.1.8 Tools for describing a sequence of Axi4Lite commands. 2021-01-14 17:43:30
risktools 0.1.0 Python implementation of the R package RTL 2020-12-05 22:01:34
scratchip 0.2.2 ScratChip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier. 2020-07-22 01:57:47
HdlLib 0.1.1 VHDL source management : parse, organize, assemble, generate testbenches 2017-07-10 14:41:42
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