# AnyV-Registers - Hardware register bank generator
Raw data
{
"_id": null,
"home_page": "https://github.com/Louis-DR/AnyV-Registers",
"name": "anyv-registers",
"maintainer": "",
"docs_url": null,
"requires_python": "",
"maintainer_email": "",
"keywords": "verilog,register,generator,fpga,asic,semiconductor,microelectronics,hardware,jinja2",
"author": "Louis Duret-Robert",
"author_email": "louisduret@gmail.com",
"download_url": "",
"platform": null,
"description": "# AnyV-Registers - Hardware register bank generator\n",
"bugtrack_url": null,
"license": "MIT",
"summary": "A template-based hardware register bank generator",
"version": "0.1.0",
"project_urls": {
"Homepage": "https://github.com/Louis-DR/AnyV-Registers"
},
"split_keywords": [
"verilog",
"register",
"generator",
"fpga",
"asic",
"semiconductor",
"microelectronics",
"hardware",
"jinja2"
],
"urls": [
{
"comment_text": "",
"digests": {
"blake2b_256": "7591621865f9360f1a341dd87afe462f8f6bf6029595f5aa92306ad463aef524",
"md5": "3bce6af2ad4a3838ca4417758f5c1666",
"sha256": "737a9edd76d753f8923cf9da0bf7db807cd283ffcf63b3d5632aaa597e1777fe"
},
"downloads": -1,
"filename": "anyv_registers-0.1.0-py3-none-any.whl",
"has_sig": false,
"md5_digest": "3bce6af2ad4a3838ca4417758f5c1666",
"packagetype": "bdist_wheel",
"python_version": "py3",
"requires_python": null,
"size": 6288,
"upload_time": "2024-02-25T13:44:24",
"upload_time_iso_8601": "2024-02-25T13:44:24.387065Z",
"url": "https://files.pythonhosted.org/packages/75/91/621865f9360f1a341dd87afe462f8f6bf6029595f5aa92306ad463aef524/anyv_registers-0.1.0-py3-none-any.whl",
"yanked": false,
"yanked_reason": null
}
],
"upload_time": "2024-02-25 13:44:24",
"github": true,
"gitlab": false,
"bitbucket": false,
"codeberg": false,
"github_user": "Louis-DR",
"github_project": "AnyV-Registers",
"travis_ci": false,
"coveralls": false,
"github_actions": false,
"lcname": "anyv-registers"
}