| Name | cengal-cpu-info JSON |
| Version |
2.0.1
JSON |
| download |
| home_page | |
| Summary | Extended, cached CPU info with consistent output format |
| upload_time | 2023-11-22 21:40:42 |
| maintainer | |
| docs_url | None |
| author | |
| requires_python | >=3.8 |
| license | |
| keywords |
cengal
cpu
hardware
info
|
| VCS |
 |
| bugtrack_url |
|
| requirements |
No requirements were recorded.
|
| Travis-CI |
No Travis.
|
| coveralls test coverage |
No coveralls.
|
# cengal_cpu_info
Extended, cached CPU info with consistent output format.
# Advantages
Consistent output format of memory-related values (unlike backend 'py-cpuinfo' package). Provides additional information. Provides cached instance (backend 'py-cpuinfo' package requires several seconds per an each call to gather CPU information).
# Installation
```bash
pip install cengal_cpu_info
```
# Documentation
## Import
```python
from cengal_cpu_info import cpu_info, CpuInfo
```
## Cached instance
```python
ci: CpuInfo = cpu_info()
```
## Methods
```python
print(f'{ci.is_arm=}')
print(f'{ci.is_x86=}')
print(f'{ci.cores_num=}')
print(f'{ci.virtual_cores_num=}')
print(f'{ci.l2_cache_size_per_core=}')
print(f'{ci.l2_cache_size_per_virtual_core=}')
print(f'{ci.l3_cache_size_per_core=}')
print(f'{ci.l3_cache_size_per_virtual_core=}')
print(f'{ci.arch=}')
print(f'{ci.arch_string_raw=}')
print(f'{ci.bits=}')
print(f'{ci.brand_raw=}')
print(f'{ci.count=}')
print(f'{ci.cpuinfo_version=}')
print(f'{ci.cpuinfo_version_string=}')
print(f'{ci.family=}')
print(f'{ci.flags=}')
print(f'{ci.hardware_raw=}')
print(f'{ci.hz_actual=}')
print(f'{ci.hz_actual_friendly=}')
print(f'{ci.hz_advertised=}')
print(f'{ci.l1_data_cache_size=}')
print(f'{ci.l1_instruction_cache_size=}')
print(f'{ci.l2_cache_associativity=}')
print(f'{ci.l2_cache_line_size=}')
print(f'{ci.l2_cache_size=}')
print(f'{ci.l3_cache_size=}')
print(f'{ci.model=}')
print(f'{ci.processor_type=}')
print(f'{ci.python_hz_advertised_friendlyversion=}')
print(f'{ci.python_version=}')
print(f'{ci.stepping=}')
print(f'{ci.vendor_id_raw=}')
```
## Example output
```python
ci.is_arm=False
ci.is_x86=True
ci.cores_num=4
ci.virtual_cores_num=4
ci.l2_cache_size_per_core=262144
ci.l2_cache_size_per_virtual_core=262144
ci.l3_cache_size_per_core=1572864
ci.l3_cache_size_per_virtual_core=1572864
ci.arch='X86_64'
ci.arch_string_raw='x86_64'
ci.bits=64
ci.brand_raw='Intel(R) Core(TM) i5-3570 CPU @ 3.40GHz'
ci.count=4
ci.cpuinfo_version=[9, 0, 0]
ci.cpuinfo_version_string='9.0.0'
ci.family=6
ci.flags=['aes', 'apic', 'arch_capabilities', 'arch_perfmon', 'avx', 'clflush', 'cmov', 'constant_tsc', 'cpuid', 'cx16', 'cx8', 'de', 'erms', 'f16c', 'flush_l1d', 'fpu', 'fsgsbase', 'fxsr', 'ht', 'hypervisor', 'ibpb', 'ibrs', 'lahf_lm', 'lm', 'mca', 'mce', 'md_clear', 'mmx', 'msr', 'mtrr', 'nopl', 'nx', 'osxsave', 'pae', 'pat', 'pcid', 'pclmulqdq', 'pdcm', 'pge', 'pni', 'popcnt', 'pse', 'pse36', 'pti', 'rdrand', 'rdrnd', 'rdtscp', 'rep_good', 'sep', 'smep', 'ss', 'ssbd', 'sse', 'sse2', 'sse4_1', 'sse4_2', 'ssse3', 'stibp', 'syscall', 'tsc', 'vme', 'xsave', 'xsaveopt', 'xtopology']
ci.hardware_raw=''
ci.hz_actual=[3403348000, 0]
ci.hz_actual_friendly='3.4033 GHz'
ci.hz_advertised=[3400000000, 0]
ci.l1_data_cache_size=131072
ci.l1_instruction_cache_size=131072
ci.l2_cache_associativity=6
ci.l2_cache_line_size=256
ci.l2_cache_size=1048576
ci.l3_cache_size=6291456
ci.model=58
ci.processor_type=0
ci.python_hz_advertised_friendlyversion='3.4000 GHz'
ci.python_version='3.8.10.final.0 (64 bit)'
ci.stepping=9
ci.vendor_id_raw='GenuineIntel'
```
# Based on Cengal
Represents part of Cengal library:
* https://pypi.org/project/cengal/
* https://github.com/FI-Mihej/Cengal
An equivalent import:
```python
from cengal.hardware.info.cpu import cpu_info, CpuInfo
```
Cengal library can be installed by:
```bash
pip install cengal
```
# Projects using Cengal
* [flet_async](https://github.com/FI-Mihej/flet_async) - wrapper which makes [Flet](https://github.com/flet-dev/flet) async and brings booth Cengal.coroutines and asyncio to Flet (Flutter based UI)
* [justpy_containers](https://github.com/FI-Mihej/justpy_containers) - wrapper around [JustPy](https://github.com/justpy-org/justpy) in order to bring more security and more production-needed features to JustPy (VueJS based UI)
* [Bensbach](https://github.com/FI-Mihej/Bensbach) - decompiler from Unreal Engine 3 bytecode to a Lisp-like script and compiler back to Unreal Engine 3 bytecode. Made for a game modding purposes
* [Realistic-Damage-Model-mod-for-Long-War](https://github.com/FI-Mihej/Realistic-Damage-Model-mod-for-Long-War) - Mod for both the original XCOM:EW and the mod Long War. Was made with a Bensbach, which was made with Cengal
* [SmartCATaloguer.com](http://www.smartcataloguer.com/index.html) - TagDB based catalog of images (tags), music albums (genre tags) and apps (categories)
# License
Copyright © 2012-2023 ButenkoMS. All rights reserved.
Licensed under the Apache License, Version 2.0.
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"description": "# cengal_cpu_info\n\nExtended, cached CPU info with consistent output format.\n\n# Advantages\n\nConsistent output format of memory-related values (unlike backend 'py-cpuinfo' package). Provides additional information. Provides cached instance (backend 'py-cpuinfo' package requires several seconds per an each call to gather CPU information).\n\n# Installation\n\n```bash\npip install cengal_cpu_info\n```\n\n# Documentation\n\n## Import\n\n```python\nfrom cengal_cpu_info import cpu_info, CpuInfo\n```\n\n## Cached instance\n\n```python\nci: CpuInfo = cpu_info()\n```\n\n## Methods\n\n```python\nprint(f'{ci.is_arm=}')\nprint(f'{ci.is_x86=}')\nprint(f'{ci.cores_num=}')\nprint(f'{ci.virtual_cores_num=}')\nprint(f'{ci.l2_cache_size_per_core=}')\nprint(f'{ci.l2_cache_size_per_virtual_core=}')\nprint(f'{ci.l3_cache_size_per_core=}')\nprint(f'{ci.l3_cache_size_per_virtual_core=}')\nprint(f'{ci.arch=}')\nprint(f'{ci.arch_string_raw=}')\nprint(f'{ci.bits=}')\nprint(f'{ci.brand_raw=}')\nprint(f'{ci.count=}')\nprint(f'{ci.cpuinfo_version=}')\nprint(f'{ci.cpuinfo_version_string=}')\nprint(f'{ci.family=}')\nprint(f'{ci.flags=}')\nprint(f'{ci.hardware_raw=}')\nprint(f'{ci.hz_actual=}')\nprint(f'{ci.hz_actual_friendly=}')\nprint(f'{ci.hz_advertised=}')\nprint(f'{ci.l1_data_cache_size=}')\nprint(f'{ci.l1_instruction_cache_size=}')\nprint(f'{ci.l2_cache_associativity=}')\nprint(f'{ci.l2_cache_line_size=}')\nprint(f'{ci.l2_cache_size=}')\nprint(f'{ci.l3_cache_size=}')\nprint(f'{ci.model=}')\nprint(f'{ci.processor_type=}')\nprint(f'{ci.python_hz_advertised_friendlyversion=}')\nprint(f'{ci.python_version=}')\nprint(f'{ci.stepping=}')\nprint(f'{ci.vendor_id_raw=}')\n```\n\n## Example output\n\n```python\nci.is_arm=False\nci.is_x86=True\nci.cores_num=4\nci.virtual_cores_num=4\nci.l2_cache_size_per_core=262144\nci.l2_cache_size_per_virtual_core=262144\nci.l3_cache_size_per_core=1572864\nci.l3_cache_size_per_virtual_core=1572864\nci.arch='X86_64'\nci.arch_string_raw='x86_64'\nci.bits=64\nci.brand_raw='Intel(R) Core(TM) i5-3570 CPU @ 3.40GHz'\nci.count=4\nci.cpuinfo_version=[9, 0, 0]\nci.cpuinfo_version_string='9.0.0'\nci.family=6\nci.flags=['aes', 'apic', 'arch_capabilities', 'arch_perfmon', 'avx', 'clflush', 'cmov', 'constant_tsc', 'cpuid', 'cx16', 'cx8', 'de', 'erms', 'f16c', 'flush_l1d', 'fpu', 'fsgsbase', 'fxsr', 'ht', 'hypervisor', 'ibpb', 'ibrs', 'lahf_lm', 'lm', 'mca', 'mce', 'md_clear', 'mmx', 'msr', 'mtrr', 'nopl', 'nx', 'osxsave', 'pae', 'pat', 'pcid', 'pclmulqdq', 'pdcm', 'pge', 'pni', 'popcnt', 'pse', 'pse36', 'pti', 'rdrand', 'rdrnd', 'rdtscp', 'rep_good', 'sep', 'smep', 'ss', 'ssbd', 'sse', 'sse2', 'sse4_1', 'sse4_2', 'ssse3', 'stibp', 'syscall', 'tsc', 'vme', 'xsave', 'xsaveopt', 'xtopology']\nci.hardware_raw=''\nci.hz_actual=[3403348000, 0]\nci.hz_actual_friendly='3.4033 GHz'\nci.hz_advertised=[3400000000, 0]\nci.l1_data_cache_size=131072\nci.l1_instruction_cache_size=131072\nci.l2_cache_associativity=6\nci.l2_cache_line_size=256\nci.l2_cache_size=1048576\nci.l3_cache_size=6291456\nci.model=58\nci.processor_type=0\nci.python_hz_advertised_friendlyversion='3.4000 GHz'\nci.python_version='3.8.10.final.0 (64 bit)'\nci.stepping=9\nci.vendor_id_raw='GenuineIntel'\n```\n\n# Based on Cengal\n\nRepresents part of Cengal library:\n* https://pypi.org/project/cengal/\n* https://github.com/FI-Mihej/Cengal\n\nAn equivalent import:\n```python\nfrom cengal.hardware.info.cpu import cpu_info, CpuInfo\n```\n\nCengal library can be installed by:\n\n```bash\npip install cengal\n```\n\n\n# Projects using Cengal\n\n* [flet_async](https://github.com/FI-Mihej/flet_async) - wrapper which makes [Flet](https://github.com/flet-dev/flet) async and brings booth Cengal.coroutines and asyncio to Flet (Flutter based UI)\n* [justpy_containers](https://github.com/FI-Mihej/justpy_containers) - wrapper around [JustPy](https://github.com/justpy-org/justpy) in order to bring more security and more production-needed features to JustPy (VueJS based UI)\n* [Bensbach](https://github.com/FI-Mihej/Bensbach) - decompiler from Unreal Engine 3 bytecode to a Lisp-like script and compiler back to Unreal Engine 3 bytecode. Made for a game modding purposes\n* [Realistic-Damage-Model-mod-for-Long-War](https://github.com/FI-Mihej/Realistic-Damage-Model-mod-for-Long-War) - Mod for both the original XCOM:EW and the mod Long War. Was made with a Bensbach, which was made with Cengal\n* [SmartCATaloguer.com](http://www.smartcataloguer.com/index.html) - TagDB based catalog of images (tags), music albums (genre tags) and apps (categories)\n\n# License\n\nCopyright \u00a9 2012-2023 ButenkoMS. All rights reserved.\n\nLicensed under the Apache License, Version 2.0.\n",
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