# cheap_pie
A python tool for register-based chip verification and validation
"Cheap Pie" is a python tool for register-based chip verification and validation.
The name is a translitteration of "chip py" for obvious reasons.
Given an input description file for the chip, it provides a register-level and
bitfield-level read/write access, through a generic transport layer.
Currently the implemented description input modes are:
- CMSIS-SVD (https://www.keil.com/pack/doc/CMSIS/SVD/html/svd_Format_pg.html)
- IP-XACT ( https://www.accellera.org/downloads/standards/ip-xact )
- SystemRDL (https://www.accellera.org/activities/working-groups/systemrdl)
but it should be relatively easy to add different chip description formats.
Although tested on few real chips (NXP QN9080, I.MX RT1010, K64F),
cheap_pie parser already supports dozen of devices, listed in the CMSIS-SVD
repository https://github.com/posborne/cmsis-svd .
Currently the supported transport layers are jlink and pyocd, but it should be really easy
to add support for different transport layers, like for instance openSDA,
CMSIS-DAP, Total Phase Cheetah, GDB or any other.
Experimental support for pyverilator transport allows to run interactive simulation
of register blocks generated from SystemRDL source.
Author: Marco Merlin
Tested on ipython3 (python 3.8.5) on ubuntu 20.04
# IPython Example:
%run cheap_pie
inval = "0xFFFFFFFF"
hal.regs.ADC_ANA_CTRL.setreg(inval)
retval = hex(hal.regs.ADC_ANA_CTRL.getreg())
assert(literal_eval(inval) == literal_eval(retval))
# decimal assignement
inval = 2
hal.regs.ADC_ANA_CTRL.setreg(inval)
retval = hal.regs.ADC_ANA_CTRL.getreg()
assert(inval == retval)
hal.regs.ADC_ANA_CTRL
hal.regs.ADC_ANA_CTRL.display()
print('Test bitfield methods...')
hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM
hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.display()
hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.display(2)
hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.setbit(inval)
retval = hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.getbit()
assert(inval == retval)
# subscriptable register access
hal[0]
# subscriptable bitfield access
hal[0][0]
# subscriptable as a dictionary
hal['SYSCON_RST_SW_SET']
hal['ADC_ANA_CTRL']['ADC_BM']
# assignement
hal['ADC_ANA_CTRL'] = 1
hal['ADC_ANA_CTRL']['ADC_BM'] = 2
# dict-based assignement in single register write
hal['ADC_ANA_CTRL'] = {'DITHER_EN': 1, 'CHOP_EN': 1, 'INV_CLK': 1}
# help
hal.regs.ADC_ANA_CTRL.help()
ADC core and reference setting regsiter
ADC_BM:
: ADC bias current selection.
ADC_ORDER:
: 1 to enable SD ADC 2 order mode selection
DITHER_EN:
: 1 to enable SD ADC PN Sequence in chopper mode
CHOP_EN:
: 1 to enable SD ADC chopper
INV_CLK:
: 1 to invert SD ADC Output Clock
VREF_BM:
: SD ADC Reference Driver bias current selection.
VREF_BM_X3:
: SD ADC Reference Driver bias current triple.
VINN_IN_BM:
: PGA VlNN Input Driver bias current selection.
VINN_OUT_BM:
: PGA VlNN Output Driver bias current selection.
VINN_OUT_BM_X3:
: PGA VlNN Output Driver bias current triple.
ADC_BM_DIV2:
: SD ADC bias current half.
# CLI Example:
# load RT1010 from local svd file under ./devices/
# automatically calls ipython and cheap_pie initialization
./cheap_pie.sh -rf MIMXRT1011.svd -t jlink
# load K64 from CMSIS-SVD
# need to specify vendor for svd not in ./devices/
./cheap_pie.sh -rf MK64F12.svd -ve Freescale -t jlink
# calls QN9080 with dummy transport layer
# useful to explore device registers
./cheap_pie.sh -t dummy
# Default configurations Examples:
# calls QN9080 device with dummy transport layer
./cfgs/cp_qn9080_dummy.sh
# calls RT1010 device with jlink transport layer
./cfgs/cp_rt1010_jlink.sh
# calls K20 device with dummy transport layer
./cfgs/cp_k20_dummy.sh
# Verilator interactive simulation Examples:
./tools/rdl2verilog.py -f ./devices/rdl/basic.rdl
./cheap_pie.sh -dd ./devices/rdl -rf basic.rdl -fmt rdl -t verilator -topv ./devices/rdl/basic/basic_rf.sv
# Install
## From pypi
pip3 install cheap_pie
## From github
pip3 install git+https://github.com/bat52/cheap_pie.git@master
# Dependencies for core (required):
# for XML parsing (used by legacy svd parser and IP-XACT parser)
pip3 install untangle
# for exporting XML info into a human-readable document
pip3 install python-docx
# for dumping registers
pip3 install hickle
# CMSIS-SVD python parser including many svd files https://github.com/posborne/cmsis-svd
pip3 install cmsis-svd
# SPIRIT IP-XACT parser through ipyxact https://github.com/olofk/ipyxact
pip3 install ipyxact
# SystemRDL to register-file verilog
https://github.com/hughjackson/PeakRDL-verilog
# SystemRDL to IP-XACT
https://github.com/SystemRDL/PeakRDL-ipxact
# Dependencies for validation/transport layers (optional):
# for JLINK
pip3 install pylink-square
# pyOCD for CMSIS-DAP and JLINK support (only tested in python-venv)
pip3 install pyocd
# esptool for Espressif devices (not yet functional)
pip3 install esptool
# Dependencies for verification (optional AND experimental):
# verilator
https://www.veripool.org/verilator/
# pyverilator (python verilator wrapper)
https://github.com/csail-csg/pyverilator
# gtkwave
http://gtkwave.sourceforge.net/
# Register description formats
regtool from opentitan project seems similar, using JSON to represent chip/IP structure, and I2C transport
https://docs.opentitan.org/doc/rm/register_tool/
custom input, output: verilog, VHDL, YAML, JSON, TOML, Spreadsheet (XLSX, XLS, OSD, CSV)
https://github.com/rggen/rggen
convert ipxact register file description into verilog register bank
https://github.com/oddball/ipxact2systemverilog
# Others
In conjunction with pyVISA (https://pyvisa.readthedocs.io/en/master/), used for
instument control, it provides a simple and fully python-contained environment
for silicon validation.
Graphical Render of bitfield structures
https://github.com/wavedrom/bitfield
C++ register/bitfields access (including generation from svd)
https://github.com/thanks4opensource/regbits
STM C++ regbits implementation
https://github.com/thanks4opensource/regbits_stm
a barebone embedded library generator
https://modm.io/
hardware descriptions for AVR and STM32 devices
https://github.com/modm-io/modm-devices
STM32 Peripheral Access Crates (from svd)
https://github.com/stm32-rs/stm32-rs
Banner created with pyfiglet
https://www.devdungeon.com/content/create-ascii-art-text-banners-python#install_pyfiglet
Cheap Pie is modeled after an original Octave/Matlab implementation that cannot
be shared due to licensing reasons. The original code was converted to python
using SMOP ( https://github.com/ripple-neuro/smop ).
Raw data
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"description": "# cheap_pie\nA python tool for register-based chip verification and validation\n\n\"Cheap Pie\" is a python tool for register-based chip verification and validation.\nThe name is a translitteration of \"chip py\" for obvious reasons.\n\nGiven an input description file for the chip, it provides a register-level and \nbitfield-level read/write access, through a generic transport layer.\n\nCurrently the implemented description input modes are:\n- CMSIS-SVD (https://www.keil.com/pack/doc/CMSIS/SVD/html/svd_Format_pg.html)\n- IP-XACT ( https://www.accellera.org/downloads/standards/ip-xact )\n- SystemRDL (https://www.accellera.org/activities/working-groups/systemrdl)\n\nbut it should be relatively easy to add different chip description formats.\n\nAlthough tested on few real chips (NXP QN9080, I.MX RT1010, K64F),\ncheap_pie parser already supports dozen of devices, listed in the CMSIS-SVD \nrepository https://github.com/posborne/cmsis-svd .\n\nCurrently the supported transport layers are jlink and pyocd, but it should be really easy\nto add support for different transport layers, like for instance openSDA, \nCMSIS-DAP, Total Phase Cheetah, GDB or any other.\n\nExperimental support for pyverilator transport allows to run interactive simulation\nof register blocks generated from SystemRDL source.\n\nAuthor: Marco Merlin\nTested on ipython3 (python 3.8.5) on ubuntu 20.04\n\n# IPython Example:\n %run cheap_pie\n inval = \"0xFFFFFFFF\"\n hal.regs.ADC_ANA_CTRL.setreg(inval)\n retval = hex(hal.regs.ADC_ANA_CTRL.getreg())\n assert(literal_eval(inval) == literal_eval(retval))\n\n # decimal assignement \n inval = 2\n hal.regs.ADC_ANA_CTRL.setreg(inval)\n retval = hal.regs.ADC_ANA_CTRL.getreg() \n assert(inval == retval)\n \n hal.regs.ADC_ANA_CTRL\n hal.regs.ADC_ANA_CTRL.display()\n \n print('Test bitfield methods...')\n \n hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM\n hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.display()\n hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.display(2)\n hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.setbit(inval)\n retval = hal.regs.ADC_ANA_CTRL.bitfields.ADC_BM.getbit()\n assert(inval == retval)\n\n # subscriptable register access\n hal[0]\n # subscriptable bitfield access\n hal[0][0]\n # subscriptable as a dictionary\n hal['SYSCON_RST_SW_SET']\n hal['ADC_ANA_CTRL']['ADC_BM']\n \n # assignement\n hal['ADC_ANA_CTRL'] = 1\n hal['ADC_ANA_CTRL']['ADC_BM'] = 2\n # dict-based assignement in single register write\n hal['ADC_ANA_CTRL'] = {'DITHER_EN': 1, 'CHOP_EN': 1, 'INV_CLK': 1}\n\n # help\n hal.regs.ADC_ANA_CTRL.help()\n ADC core and reference setting regsiter\n ADC_BM: \n : ADC bias current selection.\n ADC_ORDER: \n : 1 to enable SD ADC 2 order mode selection\n DITHER_EN: \n : 1 to enable SD ADC PN Sequence in chopper mode\n CHOP_EN: \n : 1 to enable SD ADC chopper\n INV_CLK: \n : 1 to invert SD ADC Output Clock\n VREF_BM: \n : SD ADC Reference Driver bias current selection.\n VREF_BM_X3: \n : SD ADC Reference Driver bias current triple.\n VINN_IN_BM: \n : PGA VlNN Input Driver bias current selection.\n VINN_OUT_BM: \n : PGA VlNN Output Driver bias current selection.\n VINN_OUT_BM_X3: \n : PGA VlNN Output Driver bias current triple.\n ADC_BM_DIV2: \n : SD ADC bias current half.\n\n# CLI Example:\n # load RT1010 from local svd file under ./devices/\n # automatically calls ipython and cheap_pie initialization\n ./cheap_pie.sh -rf MIMXRT1011.svd -t jlink\n\n # load K64 from CMSIS-SVD\n # need to specify vendor for svd not in ./devices/\n ./cheap_pie.sh -rf MK64F12.svd -ve Freescale -t jlink\n\n # calls QN9080 with dummy transport layer \n # useful to explore device registers\n ./cheap_pie.sh -t dummy\n\n# Default configurations Examples:\n # calls QN9080 device with dummy transport layer\n ./cfgs/cp_qn9080_dummy.sh\n # calls RT1010 device with jlink transport layer\n ./cfgs/cp_rt1010_jlink.sh\n # calls K20 device with dummy transport layer\n ./cfgs/cp_k20_dummy.sh\n\n# Verilator interactive simulation Examples:\n ./tools/rdl2verilog.py -f ./devices/rdl/basic.rdl\n ./cheap_pie.sh -dd ./devices/rdl -rf basic.rdl -fmt rdl -t verilator -topv ./devices/rdl/basic/basic_rf.sv\n\n# Install\n## From pypi\n pip3 install cheap_pie\n## From github\n pip3 install git+https://github.com/bat52/cheap_pie.git@master\n\n# Dependencies for core (required): \n # for XML parsing (used by legacy svd parser and IP-XACT parser)\n pip3 install untangle\n # for exporting XML info into a human-readable document\n pip3 install python-docx\n # for dumping registers\n pip3 install hickle\n # CMSIS-SVD python parser including many svd files https://github.com/posborne/cmsis-svd\n pip3 install cmsis-svd\n # SPIRIT IP-XACT parser through ipyxact https://github.com/olofk/ipyxact\n pip3 install ipyxact \n # SystemRDL to register-file verilog\n https://github.com/hughjackson/PeakRDL-verilog\n # SystemRDL to IP-XACT\n https://github.com/SystemRDL/PeakRDL-ipxact\n# Dependencies for validation/transport layers (optional): \n # for JLINK\n pip3 install pylink-square\n # pyOCD for CMSIS-DAP and JLINK support (only tested in python-venv)\n pip3 install pyocd\n # esptool for Espressif devices (not yet functional)\n pip3 install esptool \n# Dependencies for verification (optional AND experimental):\n # verilator\n https://www.veripool.org/verilator/\n # pyverilator (python verilator wrapper)\n https://github.com/csail-csg/pyverilator \n # gtkwave\n http://gtkwave.sourceforge.net/\n\n# Register description formats\nregtool from opentitan project seems similar, using JSON to represent chip/IP structure, and I2C transport\nhttps://docs.opentitan.org/doc/rm/register_tool/\n\ncustom input, output: verilog, VHDL, YAML, JSON, TOML, Spreadsheet (XLSX, XLS, OSD, CSV)\nhttps://github.com/rggen/rggen\n\nconvert ipxact register file description into verilog register bank\nhttps://github.com/oddball/ipxact2systemverilog\n\n# Others\t\nIn conjunction with pyVISA (https://pyvisa.readthedocs.io/en/master/), used for \ninstument control, it provides a simple and fully python-contained environment\nfor silicon validation.\n\nGraphical Render of bitfield structures\nhttps://github.com/wavedrom/bitfield\n\nC++ register/bitfields access (including generation from svd)\nhttps://github.com/thanks4opensource/regbits\n\nSTM C++ regbits implementation\nhttps://github.com/thanks4opensource/regbits_stm\n\na barebone embedded library generator\nhttps://modm.io/\n\nhardware descriptions for AVR and STM32 devices\nhttps://github.com/modm-io/modm-devices\n\nSTM32 Peripheral Access Crates (from svd)\nhttps://github.com/stm32-rs/stm32-rs\n\nBanner created with pyfiglet\nhttps://www.devdungeon.com/content/create-ascii-art-text-banners-python#install_pyfiglet\n\nCheap Pie is modeled after an original Octave/Matlab implementation that cannot\nbe shared due to licensing reasons. The original code was converted to python\nusing SMOP ( https://github.com/ripple-neuro/smop ).\n",
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