| Name | digsim-logic-simulator JSON |
| Version |
0.4.0
JSON |
| download |
| home_page | None |
| Summary | Interactive Digital Logic Simulator |
| upload_time | 2024-04-10 15:52:36 |
| maintainer | None |
| docs_url | None |
| author | None |
| requires_python | >=3.8 |
| license | The Clear BSD License Copyright (c) 2023, Fredrik Andersson All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------------------------------------- |
| keywords |
educational
simulation
digital
|
| VCS |
 |
| bugtrack_url |
|
| requirements |
No requirements were recorded.
|
| Travis-CI |
No Travis.
|
| coveralls test coverage |
No coveralls.
|
# DigSim - Interactive Digital Logic Simulator
<p align="center">
<img alt="The DigSim Application" src="https://raw.githubusercontent.com/freand76/digsim/af1bf95eb16d1af19f26159a4c1e1b88565703d7/docs/images/screenshot_digsim_app.png" width=85%>
</p>
## Introduction
DigSim is a python based framework for digital circuit simulation.
The main purpose of the software is to, in an educational way, play around with digital logic (simple gates and verilog designs).
When working with block design in Verilog/VHDL the simulation tools are normally fed with test stimuli (a very non-interactive way of working...)
A block design can be synthesized and tested on an FPGA (where there are possibilities for interactivity if buttons and LED/Hex digits are available),
but that often has a great cost in time (and sometimes money) leading to long turnaround time.
I started developing DigSim to make it easy to implement and visualize the functionality of simple verlog modules.
During development I tried to synthesize larger verilog designs, such as the classic [6502 CPU](https://en.wikipedia.org/wiki/MOS_Technology_6502),
and even if it is slower than many other simulators it is not entirely useless.
### Features
* Create and simulate a circuit using python code
* Create and simulate a circuit **interactively** using the GUI
* Create new components using synthesized verilog code
* Save simulation results in VCD files, which can be opened in for example GTKWave.
## Quickstart
### Install from PyPi
```
pip3 install digsim-logic-simulator
```
### Install from GitHub
```
> git clone https://github.com/freand76/digsim.git
> cd digsim
> python3 -m pip install .
```
### Start Interactive GUI
```
> python3 -m digsim.app
```
**Note: Ubuntu**
If your Ubuntu installation gives the folloing error message:
*qt.qpa.plugin: Could not load the Qt platform plugin "xcb" in "" even though it was found.*
*This application failed to start because no Qt platform plugin could be initialized. Reinstalling the application may fix this problem.*
*Available platform plugins are: vnc, wayland, wayland-egl, eglfs, offscreen, xcb, minimal, linuxfb, vkkhrdisplay, minimalegl.*
Then the following package must be installed:
```
> apt install libxcb-cursor0
```
### Start with example circuit (example circuits are available in the github repository)
```
> python3 -m digsim.app --load example_circuits/counter_yosys_netlist.circuit
```
### Run example (examples are available in the github repository)
```
> python3 examples/example_sr.py
```
### Look at waveforms
```
> python3 examples/example_sr.py
> gtkwave sr.vcd
```
## Yosys synthesis helper tool
```
> python3 -m digsim.synth synth -i <verilog file 1> <optional verilog file 2> -o <output_file.json> -t <verilog top_module>
```
## Documentation
[Documentation](https://github.com/freand76/digsim/blob/main/docs/documentation.md) on GitHub
## Star History
[](https://star-history.com/#freand76/digsim&Date)
Raw data
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"description": "# DigSim - Interactive Digital Logic Simulator\n\n\n\n\n\n<p align=\"center\">\n <img alt=\"The DigSim Application\" src=\"https://raw.githubusercontent.com/freand76/digsim/af1bf95eb16d1af19f26159a4c1e1b88565703d7/docs/images/screenshot_digsim_app.png\" width=85%>\n</p>\n\n## Introduction\n\nDigSim is a python based framework for digital circuit simulation.\nThe main purpose of the software is to, in an educational way, play around with digital logic (simple gates and verilog designs).\n\nWhen working with block design in Verilog/VHDL the simulation tools are normally fed with test stimuli (a very non-interactive way of working...)\nA block design can be synthesized and tested on an FPGA (where there are possibilities for interactivity if buttons and LED/Hex digits are available),\nbut that often has a great cost in time (and sometimes money) leading to long turnaround time.\n\nI started developing DigSim to make it easy to implement and visualize the functionality of simple verlog modules.\nDuring development I tried to synthesize larger verilog designs, such as the classic [6502 CPU](https://en.wikipedia.org/wiki/MOS_Technology_6502),\nand even if it is slower than many other simulators it is not entirely useless.\n\n### Features\n * Create and simulate a circuit using python code\n * Create and simulate a circuit **interactively** using the GUI\n * Create new components using synthesized verilog code\n * Save simulation results in VCD files, which can be opened in for example GTKWave.\n\n## Quickstart\n\n### Install from PyPi\n```\npip3 install digsim-logic-simulator\n```\n\n### Install from GitHub\n```\n> git clone https://github.com/freand76/digsim.git\n> cd digsim\n> python3 -m pip install .\n```\n\n### Start Interactive GUI\n\n```\n> python3 -m digsim.app\n```\n\n**Note: Ubuntu**\n\nIf your Ubuntu installation gives the folloing error message:\n\n*qt.qpa.plugin: Could not load the Qt platform plugin \"xcb\" in \"\" even though it was found.*\n*This application failed to start because no Qt platform plugin could be initialized. Reinstalling the application may fix this problem.*\n\n*Available platform plugins are: vnc, wayland, wayland-egl, eglfs, offscreen, xcb, minimal, linuxfb, vkkhrdisplay, minimalegl.*\n\nThen the following package must be installed:\n```\n> apt install libxcb-cursor0\n```\n\n### Start with example circuit (example circuits are available in the github repository)\n```\n> python3 -m digsim.app --load example_circuits/counter_yosys_netlist.circuit\n```\n\n### Run example (examples are available in the github repository)\n```\n> python3 examples/example_sr.py\n```\n\n### Look at waveforms\n```\n> python3 examples/example_sr.py\n> gtkwave sr.vcd\n```\n\n## Yosys synthesis helper tool\n\n```\n> python3 -m digsim.synth synth -i <verilog file 1> <optional verilog file 2> -o <output_file.json> -t <verilog top_module>\n```\n\n## Documentation\n\n[Documentation](https://github.com/freand76/digsim/blob/main/docs/documentation.md) on GitHub\n\n## Star History\n\n[](https://star-history.com/#freand76/digsim&Date)\n",
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