<h1 align="center"><span style="color:red"><u>I</u></span>ntegrated <span style="color:red"><u>C</u></span>ircuit <span style="color:red"><u>Hier</u></span>archy</h1>
## 做什么用？
> 懒得写，AI 帮我总结了一下。
`ichier` 是一个用于创建和处理电路设计的 Python 库。它允许用户定义设计、模块、端口和实例，并生成对应的代码。这个库可以用于以下几个方面：
1. **设计创建**：通过 `Design` 和 `Module` 等类，可以构建电路设计，并添加多个模块来实现抽象的对应关系。
2. **终端和网络定义**：可以轻松定义模块之间的连接，通过设置输入输出端口 `Terminal` 和内部网络 `net` 来描述电路的交互。
3. **实例化模块**：允许将模块实例化多次，以便在设计中复用特定的功能，比如在一个电路中多次使用同一个逻辑门。
4. **代码解析**：支持解析 SPICE 和 Verilog 格式的电路文件，生成 `Design` 对象，方便分析电路结构和参数，提取设计信息。
5. **命令行交互**：支持在 Python 中启动交互式 shell，方便对电路的信息进行查询。
## 安装
```bash
pip install ichier -U
```
## 描述一个电路
> buffer.py
```python
from ichier import *
design = Design(
modules=[
Module(
name="inv",
terminals=[
Terminal(name="A", direction="input"),
Terminal(name="Z", direction="output"),
],
),
Module(
name="buf",
terminals=[
Terminal(
name="A",
direction="input",
),
Terminal(
name="Z",
direction="output",
),
],
nets=[
Net(name="A"),
Net(name="Z"),
Net(name="inter"),
],
instances=[
Instance(
name="i1",
reference="inv",
connection={
"A": "A",
"Z": "inter",
},
parameters={"size": "x2"},
),
Instance(
name="i2",
reference="inv",
connection={
"A": "inter",
"Z": "Z",
},
parameters={"size": "x4"},
),
],
),
],
)
```
+ 查询信息
```python
design.modules.figs
# (Module('inv'), Module('buf'))
buf = design.modules["buf"]
buf.terminals.figs
# (Terminal('A', 'input'), Terminal('Z', 'output'))
buf.instances.figs
# (Instance('i1'), Instance('i2'))
buf.nets.figs
# (Net('A'), Net('Z'), Net('inter'))
```
## 从网表读入设计
+ 解析 SPICE 文件
```python
from ichier.parser import fromSpice
design = fromSpice("top.cdl")
```
+ 解析 Verilog 文件
```python
from ichier.parser import fromVerilog
design = fromVerilog("top.v")
```
+ 也可以直接使用 CLI 工具
```shell
python -m ichier parse spice top.cdl
```
> 预先安装 `ipython` 和 `rich` 库，会有更好的交互体验。
## LICENSE
GNU Affero General Public License v3
Raw data
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"description": "<h1 align=\"center\"><span style=\"color:red\"><u>I</u></span>ntegrated <span style=\"color:red\"><u>C</u></span>ircuit <span style=\"color:red\"><u>Hier</u></span>archy</h1>\r\n\r\n## \u505a\u4ec0\u4e48\u7528\uff1f\r\n\r\n> \u61d2\u5f97\u5199\uff0cAI \u5e2e\u6211\u603b\u7ed3\u4e86\u4e00\u4e0b\u3002\r\n\r\n`ichier` \u662f\u4e00\u4e2a\u7528\u4e8e\u521b\u5efa\u548c\u5904\u7406\u7535\u8def\u8bbe\u8ba1\u7684 Python \u5e93\u3002\u5b83\u5141\u8bb8\u7528\u6237\u5b9a\u4e49\u8bbe\u8ba1\u3001\u6a21\u5757\u3001\u7aef\u53e3\u548c\u5b9e\u4f8b\uff0c\u5e76\u751f\u6210\u5bf9\u5e94\u7684\u4ee3\u7801\u3002\u8fd9\u4e2a\u5e93\u53ef\u4ee5\u7528\u4e8e\u4ee5\u4e0b\u51e0\u4e2a\u65b9\u9762\uff1a\r\n\r\n1. **\u8bbe\u8ba1\u521b\u5efa**\uff1a\u901a\u8fc7 `Design` \u548c `Module` \u7b49\u7c7b\uff0c\u53ef\u4ee5\u6784\u5efa\u7535\u8def\u8bbe\u8ba1\uff0c\u5e76\u6dfb\u52a0\u591a\u4e2a\u6a21\u5757\u6765\u5b9e\u73b0\u62bd\u8c61\u7684\u5bf9\u5e94\u5173\u7cfb\u3002\r\n2. **\u7ec8\u7aef\u548c\u7f51\u7edc\u5b9a\u4e49**\uff1a\u53ef\u4ee5\u8f7b\u677e\u5b9a\u4e49\u6a21\u5757\u4e4b\u95f4\u7684\u8fde\u63a5\uff0c\u901a\u8fc7\u8bbe\u7f6e\u8f93\u5165\u8f93\u51fa\u7aef\u53e3 `Terminal` \u548c\u5185\u90e8\u7f51\u7edc `net` \u6765\u63cf\u8ff0\u7535\u8def\u7684\u4ea4\u4e92\u3002\r\n3. **\u5b9e\u4f8b\u5316\u6a21\u5757**\uff1a\u5141\u8bb8\u5c06\u6a21\u5757\u5b9e\u4f8b\u5316\u591a\u6b21\uff0c\u4ee5\u4fbf\u5728\u8bbe\u8ba1\u4e2d\u590d\u7528\u7279\u5b9a\u7684\u529f\u80fd\uff0c\u6bd4\u5982\u5728\u4e00\u4e2a\u7535\u8def\u4e2d\u591a\u6b21\u4f7f\u7528\u540c\u4e00\u4e2a\u903b\u8f91\u95e8\u3002\r\n\r\n4. **\u4ee3\u7801\u89e3\u6790**\uff1a\u652f\u6301\u89e3\u6790 SPICE \u548c Verilog \u683c\u5f0f\u7684\u7535\u8def\u6587\u4ef6\uff0c\u751f\u6210 `Design` \u5bf9\u8c61\uff0c\u65b9\u4fbf\u5206\u6790\u7535\u8def\u7ed3\u6784\u548c\u53c2\u6570\uff0c\u63d0\u53d6\u8bbe\u8ba1\u4fe1\u606f\u3002\r\n5. **\u547d\u4ee4\u884c\u4ea4\u4e92**\uff1a\u652f\u6301\u5728 Python \u4e2d\u542f\u52a8\u4ea4\u4e92\u5f0f shell\uff0c\u65b9\u4fbf\u5bf9\u7535\u8def\u7684\u4fe1\u606f\u8fdb\u884c\u67e5\u8be2\u3002\r\n\r\n## \u5b89\u88c5\r\n\r\n```bash\r\npip install ichier -U\r\n```\r\n\r\n## \u63cf\u8ff0\u4e00\u4e2a\u7535\u8def\r\n\r\n> buffer.py\r\n\r\n```python\r\nfrom ichier import *\r\n\r\ndesign = Design(\r\n modules=[\r\n Module(\r\n name=\"inv\",\r\n terminals=[\r\n Terminal(name=\"A\", direction=\"input\"),\r\n Terminal(name=\"Z\", direction=\"output\"),\r\n ],\r\n ),\r\n Module(\r\n name=\"buf\",\r\n terminals=[\r\n Terminal(\r\n name=\"A\",\r\n direction=\"input\",\r\n ),\r\n Terminal(\r\n name=\"Z\",\r\n direction=\"output\",\r\n ),\r\n ],\r\n nets=[\r\n Net(name=\"A\"),\r\n Net(name=\"Z\"),\r\n Net(name=\"inter\"),\r\n ],\r\n instances=[\r\n Instance(\r\n name=\"i1\",\r\n reference=\"inv\",\r\n connection={\r\n \"A\": \"A\",\r\n \"Z\": \"inter\",\r\n },\r\n parameters={\"size\": \"x2\"},\r\n ),\r\n Instance(\r\n name=\"i2\",\r\n reference=\"inv\",\r\n connection={\r\n \"A\": \"inter\",\r\n \"Z\": \"Z\",\r\n },\r\n parameters={\"size\": \"x4\"},\r\n ),\r\n ],\r\n ),\r\n ],\r\n)\r\n```\r\n\r\n+ \u67e5\u8be2\u4fe1\u606f\r\n\r\n```python\r\ndesign.modules.figs\r\n# (Module('inv'), Module('buf'))\r\n\r\nbuf = design.modules[\"buf\"]\r\n\r\nbuf.terminals.figs\r\n# (Terminal('A', 'input'), Terminal('Z', 'output'))\r\n\r\nbuf.instances.figs\r\n# (Instance('i1'), Instance('i2'))\r\n\r\nbuf.nets.figs\r\n# (Net('A'), Net('Z'), Net('inter'))\r\n```\r\n\r\n## \u4ece\u7f51\u8868\u8bfb\u5165\u8bbe\u8ba1\r\n\r\n+ \u89e3\u6790 SPICE \u6587\u4ef6\r\n\r\n```python\r\nfrom ichier.parser import fromSpice\r\ndesign = fromSpice(\"top.cdl\")\r\n```\r\n\r\n+ \u89e3\u6790 Verilog \u6587\u4ef6\r\n\r\n```python\r\nfrom ichier.parser import fromVerilog\r\ndesign = fromVerilog(\"top.v\")\r\n```\r\n\r\n+ \u4e5f\u53ef\u4ee5\u76f4\u63a5\u4f7f\u7528 CLI \u5de5\u5177\r\n\r\n```shell\r\npython -m ichier parse spice top.cdl\r\n```\r\n\r\n> \u9884\u5148\u5b89\u88c5 `ipython` \u548c `rich` \u5e93\uff0c\u4f1a\u6709\u66f4\u597d\u7684\u4ea4\u4e92\u4f53\u9a8c\u3002\r\n\r\n## LICENSE\r\n\r\nGNU Affero General Public License v3\r\n",
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