# ipxact2systemverilog ipxact2rst ipxact2md ipxact2vhdl ipxact2c
[](https://circleci.com/gh/oddball/ipxact2systemverilog)
[](https://pypi.python.org/pypi/ipxact2systemverilog/)
This software takes an IP-XACT description of register banks, and
generates synthesizable VHDL and SystemVerilog packages and
ReStructuredText documents. It ONLY considers register bank
descriptions. The software does not generate OVM or UVM test bench
packages. In the example/tb directory there is an example of how to use
the generated packages.
## Usage
```bash
pip install ipxact2systemverilog
ipxact2systemverilog --srcFile FILE --destDir DIR
ipxact2rst --srcFile FILE --destDir DIR
ipxact2md --srcFile FILE --destDir DIR
ipxact2vhdl --srcFile FILE --destDir DIR
ipxact2c --srcFile FILE --destDir DIR
```
## Development
See https://github.com/oddball/ipxact2systemverilog
## Testing the example file
```bash
make
```
If Modelsim is installed: :
```bash
make compile
make sim
```
## Note
You can use <http://pandoc.org/demos.html> to convert to almost any
fileformat.
## Validation
To validate your xml :
```bash
xmllint --noout --schema ipxact2systemverilog/xml/component.xsd example/input/test.xml
```
## Dependencies
```bash
pip install docutils lxml mdutils
```
## Dependencies used by makefile
These are not needed for ipxact2systemverilog, but used for generating
some of the files in example/output
```bash
brew install pandoc
# needed for sphinx
brew install texlive
sudo tlmgr install latexmk
```
## Working in development mode for pypi
```bash
rm -rf dist
pip3 install -e .
python3 setup.py sdist
twine upload dist/*
```
## TODO
- A better test bench for the generated packages should be implemented.
- More complicated IPXACT files should be added and tried out.
- Add support for the SystemVerilog generator to have a register field
of an enumerated type.
- Support DIM
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