<!--
SPDX-FileCopyrightText: 2022 Thomas Kramer
SPDX-License-Identifier: CC-BY-SA-4.0
-->
# LibreCell - Lib
Characterization kit for CMOS cells.
This Python package comes with a some stand-alone command-line tools:
* Most notably `lctime` for *recognition* and *characterization* of combinational and sequential cells.
* `sp2bool`: Recognition ('reverse engineering') of transistor networks. This is intended for analyzis and debugging.
* `libertyviz`: Visualization of NDLM tables.
## Getting started
```
# Clone this repository.
git clone https://codeberg.org/librecell/lctime
cd lctime
# Install
./install_develop.sh
# Run tests
cd tests
./run_tests.sh
```
### Characterize a cell
An ready-to-run example can be found in the `examples` folder.
The script `run_example.sh` should characterize the `INVX1` inverter.
The following example determines the input capacitances and timing delays of a combinational cell.
It is assumed that `FreePDK45` is installed in the users home directory.
Required inputs are:
* --liberty: A template liberty file which defines how the cells should be characterized.
* --include: SPICE files or models to be included.
* --spice: A SPICE file which contains the transistor level circuit of the cell (best including extracted parasitic capacitances).
* --cell: Name of the cell to be characterized.
* --output: Output liberty file which will contain the characterization data.
Characterize a single cell:
```sh
lctime --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \
--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \
--output-loads "0.05, 0.1, 0.2, 0.4, 0.8, 1.6" \
--slew-times "0.1, 0.2, 0.4, 0.8, 1.6, 3.2" \
--spice ~/FreePDK45/osu_soc/lib/source/netlists/AND2X1.pex.netlist \
--cell AND2X1 \
--output /tmp/and2x1.lib
```
Characterize multiple cells in the same run:
```sh
lctime --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \
--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \
--output-loads "0.05, 0.1, 0.2, 0.4, 0.8, 1.6" \
--slew-times "0.1, 0.2, 0.4, 0.8, 1.6, 3.2" \
--spice ~/FreePDK45/osu_soc/lib/source/netlists/*.pex.netlist \
--cell INVX1 AND2X1 XOR2X1 \
--output /tmp/invx1_and2x1_xor2x1.lib
```
### Cell recognition
Cell types can be recognized automatically such that only a minimal
liberty file needs to be supplied.
```sh
cd examples
lctime --liberty template.lib \
--analize-cell-function \
--include gpdk45nm.m \
--spice INVX1.pex.netlist \
--cell INVX1 \
--output-loads "0.05, 0.1, 0.2, 0.4, 0.8, 1.6" \
--slew-times "0.1, 0.2, 0.4, 0.8, 1.6, 3.2" \
--output invx1.lib
```
### Sequential cells
Characterization of sequential cells involves finding hold, setup, removal and recovery constraints.
For an example see `examples/run_example_flip-flop.sh`.
### Visualization
Vizualize the result:
```sh
libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin A --table cell_rise
```
### Characterize a cell with differential inputs
Differential inputs can be specified in the liberty template with the `complementary_pin` attribute.
Only the non-inverted pin should appear in the liberty file.
Differential pairs can also be recognized based on their naming. For example if pairs are named with suffixes `_p` for
the non-inverted pin and `_n` for the inverted pin:
```sh
lctime --diff %_p,%_n ...
```
### Merging liberty files
`lctime` will output a liberty file containing only one cell. The `libertymerge` command allows to merge this kind of
output file back into the liberty template.
The following example will take `base_liberty.lib` as a template and update its `cell` entries with the data found in
the liberty files in the `characterization` directory.
```sh
libertymerge -b base_liberty.lib \
-o output_liberty.lib \
-u characterization/*.lib
```
This approach allows to run characterization runs of multiple cells independently and in parallel (e.g using `make`).
### Recognize a cell
`lctime` can recognize the boolean function of cells based on the transistor network. Besides combinational functions
also memory-loops can be found and abstracted into latches or flip-flops.
The `sp2bool` command can be used to analyze cells and dump information about their behaviour. This can be useful for debugging and verification.
Example:
```sh
# Analyze a combinational cell.
sp2bool --spice ~/FreePDK45/osu_soc/lib/files/cells.sp --cell NAND2X1
# Analyze a flip-flop with asynchronous set and reset signals.
sp2bool --spice ~/FreePDK45/osu_soc/lib/files/cells.sp --cell DFFSR
```
For cells with *differential* inputs the `--diff` argument must be used to specify differential pairs.
## Debugging
Options for increasing debugging information:
* `--debug`: increase verbosity. Will also show the path to generated SPICE files.
* `--debug-plots` plot the waveforms of all simulations to a file. Slow but sometimes useful.
* Enable very verbose trace log: set the `DEBUG_LCTIME` environment variable to `yes`
Raw data
{
"_id": null,
"home_page": null,
"name": "lctime",
"maintainer": null,
"docs_url": null,
"requires_python": ">=3.7",
"maintainer_email": null,
"keywords": "cmos, cell, characterization, vlsi, asic",
"author": null,
"author_email": "\"T. Kramer\" <code@tkramer.ch>",
"download_url": "https://files.pythonhosted.org/packages/cb/29/21be9fcec85a79c9aa8d51f179644ee3ba04d9a00f32be24cd236c81965b/lctime-0.0.24.tar.gz",
"platform": null,
"description": "<!--\nSPDX-FileCopyrightText: 2022 Thomas Kramer\n\nSPDX-License-Identifier: CC-BY-SA-4.0\n-->\n\n# LibreCell - Lib\nCharacterization kit for CMOS cells.\nThis Python package comes with a some stand-alone command-line tools:\n\n* Most notably `lctime` for *recognition* and *characterization* of combinational and sequential cells.\n* `sp2bool`: Recognition ('reverse engineering') of transistor networks. This is intended for analyzis and debugging.\n* `libertyviz`: Visualization of NDLM tables.\n\n## Getting started\n\n```\n# Clone this repository.\ngit clone https://codeberg.org/librecell/lctime\ncd lctime\n\n# Install\n./install_develop.sh\n\n# Run tests\ncd tests\n./run_tests.sh\n```\n\n### Characterize a cell\n\nAn ready-to-run example can be found in the `examples` folder.\nThe script `run_example.sh` should characterize the `INVX1` inverter.\n\nThe following example determines the input capacitances and timing delays of a combinational cell.\n\nIt is assumed that `FreePDK45` is installed in the users home directory.\n\nRequired inputs are:\n* --liberty: A template liberty file which defines how the cells should be characterized.\n* --include: SPICE files or models to be included.\n* --spice: A SPICE file which contains the transistor level circuit of the cell (best including extracted parasitic capacitances).\n* --cell: Name of the cell to be characterized.\n* --output: Output liberty file which will contain the characterization data.\n\nCharacterize a single cell:\n```sh\nlctime --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \\\n\t--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \\\n --output-loads \"0.05, 0.1, 0.2, 0.4, 0.8, 1.6\" \\\n --slew-times \"0.1, 0.2, 0.4, 0.8, 1.6, 3.2\" \\\n\t--spice ~/FreePDK45/osu_soc/lib/source/netlists/AND2X1.pex.netlist \\\n\t--cell AND2X1 \\\n\t--output /tmp/and2x1.lib\n```\n\nCharacterize multiple cells in the same run:\n```sh\nlctime --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \\\n\t--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \\\n --output-loads \"0.05, 0.1, 0.2, 0.4, 0.8, 1.6\" \\\n --slew-times \"0.1, 0.2, 0.4, 0.8, 1.6, 3.2\" \\\n\t--spice ~/FreePDK45/osu_soc/lib/source/netlists/*.pex.netlist \\\n\t--cell INVX1 AND2X1 XOR2X1 \\\n\t--output /tmp/invx1_and2x1_xor2x1.lib\n```\n\n### Cell recognition\n\nCell types can be recognized automatically such that only a minimal\nliberty file needs to be supplied.\n\n```sh\ncd examples\nlctime --liberty template.lib \\\n --analize-cell-function \\\n --include gpdk45nm.m \\\n --spice INVX1.pex.netlist \\\n --cell INVX1 \\\n --output-loads \"0.05, 0.1, 0.2, 0.4, 0.8, 1.6\" \\\n --slew-times \"0.1, 0.2, 0.4, 0.8, 1.6, 3.2\" \\\n --output invx1.lib\n```\n\n### Sequential cells\n\nCharacterization of sequential cells involves finding hold, setup, removal and recovery constraints.\n\nFor an example see `examples/run_example_flip-flop.sh`.\n\n### Visualization\n\nVizualize the result:\n```sh\nlibertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin A --table cell_rise\n```\n\n### Characterize a cell with differential inputs\n\nDifferential inputs can be specified in the liberty template with the `complementary_pin` attribute.\nOnly the non-inverted pin should appear in the liberty file.\n\nDifferential pairs can also be recognized based on their naming. For example if pairs are named with suffixes `_p` for\nthe non-inverted pin and `_n` for the inverted pin:\n\n```sh\nlctime --diff %_p,%_n ...\n```\n\n### Merging liberty files\n`lctime` will output a liberty file containing only one cell. The `libertymerge` command allows to merge this kind of\noutput file back into the liberty template.\n\nThe following example will take `base_liberty.lib` as a template and update its `cell` entries with the data found in\nthe liberty files in the `characterization` directory.\n```sh\nlibertymerge -b base_liberty.lib \\\n -o output_liberty.lib \\\n -u characterization/*.lib\n```\nThis approach allows to run characterization runs of multiple cells independently and in parallel (e.g using `make`).\n\n### Recognize a cell\n`lctime` can recognize the boolean function of cells based on the transistor network. Besides combinational functions\nalso memory-loops can be found and abstracted into latches or flip-flops.\nThe `sp2bool` command can be used to analyze cells and dump information about their behaviour. This can be useful for debugging and verification.\n\nExample:\n```sh\n# Analyze a combinational cell. \nsp2bool --spice ~/FreePDK45/osu_soc/lib/files/cells.sp --cell NAND2X1\n\n# Analyze a flip-flop with asynchronous set and reset signals.\nsp2bool --spice ~/FreePDK45/osu_soc/lib/files/cells.sp --cell DFFSR\n```\n\nFor cells with *differential* inputs the `--diff` argument must be used to specify differential pairs.\n\n\n## Debugging\nOptions for increasing debugging information:\n* `--debug`: increase verbosity. Will also show the path to generated SPICE files.\n* `--debug-plots` plot the waveforms of all simulations to a file. Slow but sometimes useful.\n* Enable very verbose trace log: set the `DEBUG_LCTIME` environment variable to `yes`\n",
"bugtrack_url": null,
"license": "AGPL-3.0-or-later",
"summary": "CMOS standard-cell characterization kit.",
"version": "0.0.24",
"project_urls": {
"Homepage": "https://codeberg.org/librecell/lctime",
"Issue Tracker": "https://codeberg.org/librecell/lctime/issues",
"Repository": "https://codeberg.org/librecell/lctime"
},
"split_keywords": [
"cmos",
" cell",
" characterization",
" vlsi",
" asic"
],
"urls": [
{
"comment_text": "",
"digests": {
"blake2b_256": "cb2921be9fcec85a79c9aa8d51f179644ee3ba04d9a00f32be24cd236c81965b",
"md5": "dcb32a149db9d3f96e0ef8ec3cc54a79",
"sha256": "1a9a75ea1b3569479953064d0430de27294e6248f3d74ee88a877c2f8211208b"
},
"downloads": -1,
"filename": "lctime-0.0.24.tar.gz",
"has_sig": false,
"md5_digest": "dcb32a149db9d3f96e0ef8ec3cc54a79",
"packagetype": "sdist",
"python_version": "source",
"requires_python": ">=3.7",
"size": 95626,
"upload_time": "2024-04-15T19:48:00",
"upload_time_iso_8601": "2024-04-15T19:48:00.411860Z",
"url": "https://files.pythonhosted.org/packages/cb/29/21be9fcec85a79c9aa8d51f179644ee3ba04d9a00f32be24cd236c81965b/lctime-0.0.24.tar.gz",
"yanked": false,
"yanked_reason": null
}
],
"upload_time": "2024-04-15 19:48:00",
"github": false,
"gitlab": false,
"bitbucket": false,
"codeberg": true,
"codeberg_user": "librecell",
"codeberg_project": "lctime",
"lcname": "lctime"
}