| Name | leap-backend JSON |
| Version |
0.1.0
JSON |
| download |
| home_page | None |
| Summary | The backend of the LEAP framework |
| upload_time | 2024-10-05 07:30:54 |
| maintainer | None |
| docs_url | None |
| author | Hanyu Wang |
| requires_python | >=3.11 |
| license | MIT License Copyright (c) 2024 Hanyu Wang Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| keywords |
high-level synthesis
verilog
system verilog
|
| VCS |
 |
| bugtrack_url |
|
| requirements |
No requirements were recorded.
|
| Travis-CI |
No Travis.
|
| coveralls test coverage |
No coveralls.
|
LEAP-Backend
============
[](https://gitpod.io/#https://github.com/Nozidoali/leap-compiler.git)
[](https://github.com/Nozidoali/leap-backend/actions/workflows/ci.yml)
<img src="./static/leap-logo2.svg" width="64" height="64" align="left" style="margin-right: 24pt;margin-left: 12pt" />
LEAP (Logic nEtwork-Aware Pipelining) is a framework for exploiting logic synthesis and technology mapping to improve the performance of high-level synthesis (HLS) tools. LEAP is implemented in Python and is open-source under the MIT license.
This is the backend for the LEAP project. It contains the folloinwg necessary algorithms to process the subject graph.
- **blif** handles the read/write of BLIF files and provides interface to manipulate the logic network.
- **cute** is a packge for cut enumeration.
- **map** is the LUT mapping algorithm with Boolean simulation.
- **milp** contains several MILP models for timing regulation whose optimization is powered by Gurobi.
Installation
------------
1. (**recommended**) Download backend as a submodule of the main project.
2. Install and use it elsewhere.
```bash
pip install -e .
```
Getting Started
---------------
The example can be executed using `python examples/mapbuf.py`. This example:
1. Takes the BLIF file `examples/add2/add2.blif` as input (synthesized from `examples/add2/add2.v`).
2. Reads the schedulability constraints from `examples/add2/add2.json`.
3. Maps the logic network to a LUT-based FPGA with `maxLeaves=3` and `clockPeriod=1ns` (1 LUT level is `0.7ns`).
4. Writes the optimized BLIF file to `examples/add2/add2_opt.blif`.
```python
if __name__ == "__main__":
from backend import *
input_file = "examples/add2/add2.blif"
input_sched_constr = "examples/add2/add2.json"
output_file = "examples/add2/add2_opt.blif"
graph = read_blif(input_file)
model = MapBufModel(graph, json.load(open(input_sched_constr)), 1, {"maxLeaves": 3})
model.solve()
model.dumpGraph(output_file)
import subprocess
# CEC check works if no buffer is inserted
# subprocess.run(f"abc -c 'cec {input_file} {output_file}'", shell=True)
subprocess.run(f"abc -c 'read {output_file}; print_stats'", shell=True)
```
An advanced example can be found in `examples/mem`. Where:
1. The DIP specifies `mem_addr` and `mem_rd_en` has the same label.
2. The CIP specifies the `mem_data` arrives at least 1 cycle after `mem_addr` and `mem_rd_en`.
Raw data
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"description": "LEAP-Backend\n============\n\n[](https://gitpod.io/#https://github.com/Nozidoali/leap-compiler.git)\n[](https://github.com/Nozidoali/leap-backend/actions/workflows/ci.yml)\n\n<img src=\"./static/leap-logo2.svg\" width=\"64\" height=\"64\" align=\"left\" style=\"margin-right: 24pt;margin-left: 12pt\" />\nLEAP (Logic nEtwork-Aware Pipelining) is a framework for exploiting logic synthesis and technology mapping to improve the performance of high-level synthesis (HLS) tools. LEAP is implemented in Python and is open-source under the MIT license.\n\n\nThis is the backend for the LEAP project. It contains the folloinwg necessary algorithms to process the subject graph.\n- **blif** handles the read/write of BLIF files and provides interface to manipulate the logic network.\n- **cute** is a packge for cut enumeration.\n- **map** is the LUT mapping algorithm with Boolean simulation.\n- **milp** contains several MILP models for timing regulation whose optimization is powered by Gurobi.\n\nInstallation\n------------\n\n1. (**recommended**) Download backend as a submodule of the main project.\n\n2. Install and use it elsewhere.\n\n```bash\npip install -e .\n```\n\nGetting Started\n---------------\n\nThe example can be executed using `python examples/mapbuf.py`. This example:\n1. Takes the BLIF file `examples/add2/add2.blif` as input (synthesized from `examples/add2/add2.v`).\n2. Reads the schedulability constraints from `examples/add2/add2.json`.\n3. Maps the logic network to a LUT-based FPGA with `maxLeaves=3` and `clockPeriod=1ns` (1 LUT level is `0.7ns`).\n4. Writes the optimized BLIF file to `examples/add2/add2_opt.blif`.\n\n```python\nif __name__ == \"__main__\":\n from backend import *\n \n input_file = \"examples/add2/add2.blif\"\n input_sched_constr = \"examples/add2/add2.json\"\n output_file = \"examples/add2/add2_opt.blif\"\n\n graph = read_blif(input_file)\n model = MapBufModel(graph, json.load(open(input_sched_constr)), 1, {\"maxLeaves\": 3})\n model.solve()\n model.dumpGraph(output_file)\n\n import subprocess\n\n # CEC check works if no buffer is inserted\n # subprocess.run(f\"abc -c 'cec {input_file} {output_file}'\", shell=True)\n subprocess.run(f\"abc -c 'read {output_file}; print_stats'\", shell=True)\n```\n\nAn advanced example can be found in `examples/mem`. Where:\n1. The DIP specifies `mem_addr` and `mem_rd_en` has the same label.\n2. The CIP specifies the `mem_data` arrives at least 1 cycle after `mem_addr` and `mem_rd_en`.\n",
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