librecell-layout


Namelibrecell-layout JSON
Version 0.0.12 PyPI version JSON
download
home_pagehttps://codeberg.org/tok/librecell
SummaryCMOS standard cell layout generator.
upload_time2021-05-21 13:16:07
maintainer
docs_urlNone
authorT. Kramer
requires_python
licenseOHL-S v2.0
keywords cmos cell generator layout klayout vlsi asic
VCS
bugtrack_url
requirements No requirements were recorded.
Travis-CI No Travis.
coveralls test coverage No coveralls.
            # LibreCell - Layout
CMOS Standard Cell layout generator.

## Getting started

See install instructions in top-project.

### Generate a layout
Generate a layout from a SPICE netlist which includes the transistor sizes:
* --output-dir: Directory which will be used to store GDS and LEF of the cell
* --tech: Python script file containing design rules and technology related data
* --netlist: A SPICE netlist containing the netlist of the cell as a sub circuit (`.subckt`).
* --cell: Name of the cell. Must match the name of the sub circuit in the SPICE netlist.

```sh
mkdir mylibrary
lclayout --output-dir mylibrary --tech examples/dummy_tech.py --netlist examples/cells.sp --cell AND2X1
```

## Adapting design rules
Design rulesi and technology related data need to be encoded in a Python script file as shown in `examples/dummy_tech.py`.
            

Raw data

            {
    "_id": null,
    "home_page": "https://codeberg.org/tok/librecell",
    "name": "librecell-layout",
    "maintainer": "",
    "docs_url": null,
    "requires_python": "",
    "maintainer_email": "",
    "keywords": "cmos cell generator layout klayout vlsi asic",
    "author": "T. Kramer",
    "author_email": "code@tkramer.ch",
    "download_url": "https://files.pythonhosted.org/packages/51/b0/49f8bfc281e12e0535d4485f2e43328512fb328879b1ffb24fbc98cd761f/librecell-layout-0.0.12.tar.gz",
    "platform": "",
    "description": "# LibreCell - Layout\nCMOS Standard Cell layout generator.\n\n## Getting started\n\nSee install instructions in top-project.\n\n### Generate a layout\nGenerate a layout from a SPICE netlist which includes the transistor sizes:\n* --output-dir: Directory which will be used to store GDS and LEF of the cell\n* --tech: Python script file containing design rules and technology related data\n* --netlist: A SPICE netlist containing the netlist of the cell as a sub circuit (`.subckt`).\n* --cell: Name of the cell. Must match the name of the sub circuit in the SPICE netlist.\n\n```sh\nmkdir mylibrary\nlclayout --output-dir mylibrary --tech examples/dummy_tech.py --netlist examples/cells.sp --cell AND2X1\n```\n\n## Adapting design rules\nDesign rulesi and technology related data need to be encoded in a Python script file as shown in `examples/dummy_tech.py`.",
    "bugtrack_url": null,
    "license": "OHL-S v2.0",
    "summary": "CMOS standard cell layout generator.",
    "version": "0.0.12",
    "split_keywords": [
        "cmos",
        "cell",
        "generator",
        "layout",
        "klayout",
        "vlsi",
        "asic"
    ],
    "urls": [
        {
            "comment_text": "",
            "digests": {
                "md5": "f1d8bd78ac37698b55422b536acfcb48",
                "sha256": "60594d706e96227f34965974768a8110dc28cd32bcf84802e72cddb704e8b503"
            },
            "downloads": -1,
            "filename": "librecell-layout-0.0.12.tar.gz",
            "has_sig": false,
            "md5_digest": "f1d8bd78ac37698b55422b536acfcb48",
            "packagetype": "sdist",
            "python_version": "source",
            "requires_python": null,
            "size": 71134,
            "upload_time": "2021-05-21T13:16:07",
            "upload_time_iso_8601": "2021-05-21T13:16:07.017834Z",
            "url": "https://files.pythonhosted.org/packages/51/b0/49f8bfc281e12e0535d4485f2e43328512fb328879b1ffb24fbc98cd761f/librecell-layout-0.0.12.tar.gz",
            "yanked": false,
            "yanked_reason": null
        }
    ],
    "upload_time": "2021-05-21 13:16:07",
    "github": false,
    "gitlab": false,
    "bitbucket": false,
    "lcname": "librecell-layout"
}
        
Elapsed time: 0.27335s