PuEDA
=====
A collection of Python tools for micro-Electronics Design Automation.
PuEDA in an acronym, but also stands for a conjugate for of the Spanish verb "poder" which means "can".
The project was born as part of a group of scripts to test the [cryptech](https://cryptech.is/) [ecdsa256](https://github.com/bat52/cryptech) IP.
# Install (from pypi)
pip3 install pueda
# Install (from github)
pip3 install git+https://github.com/bat52/pueda.git@master
# Example of simple simulation with Icarus Verilog
from pueda.edalize import icarus
icarus(simname='hello', top='hello_tb', src_dirs = ['./hello'])
# Example of simulation with Icarus Verilog
from pueda.edalize import icarus
icarus(simname='counter', top='counter_tb', src_dirs = ['./counter/rtl','./counter/tb'], iverilog_options=['-g2005-sv'])
# Example of simulation with pyverilator
from pueda.pyverilator import pyverilator_wrapper
pv = pyverilator_wrapper(fname='./counter/rtl/counter.v', src_dirs=['./counter/rtl'], command_args = [], dump_en = False)
for _ in range(16):
pv.sim.clock.tick()
print('count = %d' % pv.sim.io.count)
assert(pv.sim.io.count == 0)
# Example of synthesys with yosys
from pueda.yosys import yosys
yosys(top='counter', src_dirs = ['./counter/rtl'], synth_en=True)
# gate count available in ./work_yosys/yosys.log
# Common functions
from pueda.common import *
# list2str : convert a list of strings into a single string
# get_source_files_alldir : returns a file list from a list of directories
# get_source_files: gets all rtl source files from a directory
# get_inc_list: returns a string appending -I to the input list of directories
# get_remote_files: donwload files from an internet url
# vcd_view: visualize a vcd or fst file with gtkwave
# get_clean_work: generate a clean work direactory for a specific tool
# write_file_lines: print a file to screen
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"description": "PuEDA\n=====\nA collection of Python tools for micro-Electronics Design Automation.\n\nPuEDA in an acronym, but also stands for a conjugate for of the Spanish verb \"poder\" which means \"can\".\nThe project was born as part of a group of scripts to test the [cryptech](https://cryptech.is/) [ecdsa256](https://github.com/bat52/cryptech) IP.\n\n# Install (from pypi)\n pip3 install pueda\n\n# Install (from github)\n pip3 install git+https://github.com/bat52/pueda.git@master\n\n# Example of simple simulation with Icarus Verilog\n from pueda.edalize import icarus\n icarus(simname='hello', top='hello_tb', src_dirs = ['./hello'])\n \n# Example of simulation with Icarus Verilog\n from pueda.edalize import icarus\n icarus(simname='counter', top='counter_tb', src_dirs = ['./counter/rtl','./counter/tb'], iverilog_options=['-g2005-sv'])\n\n# Example of simulation with pyverilator\n from pueda.pyverilator import pyverilator_wrapper\n pv = pyverilator_wrapper(fname='./counter/rtl/counter.v', src_dirs=['./counter/rtl'], command_args = [], dump_en = False)\n\n for _ in range(16):\n pv.sim.clock.tick()\n print('count = %d' % pv.sim.io.count)\n assert(pv.sim.io.count == 0)\n\n# Example of synthesys with yosys\n from pueda.yosys import yosys\n yosys(top='counter', src_dirs = ['./counter/rtl'], synth_en=True)\n # gate count available in ./work_yosys/yosys.log\n\n# Common functions\n from pueda.common import * \n \n # list2str : convert a list of strings into a single string\n # get_source_files_alldir : returns a file list from a list of directories\n # get_source_files: gets all rtl source files from a directory\n # get_inc_list: returns a string appending -I to the input list of directories\n # get_remote_files: donwload files from an internet url\n # vcd_view: visualize a vcd or fst file with gtkwave\n # get_clean_work: generate a clean work direactory for a specific tool\n # write_file_lines: print a file to screen\n\n\n",
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