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<a title="edaa-org.github.io/pySVModel" href="https://edaa-org.github.io/pyEDAA.ProjectModel"><img height="80px" src="doc/_static/logo_on_dark.svg"/></a>
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[](https://edaa-org.github.io/pyEDAA.ProjectModel/)
[](LICENSE.md)
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[](https://libraries.io/github/edaa-org/pyEDAA.ProjectModel)
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[](https://www.codacy.com/gh/edaa-org/pyEDAA.ProjectModel)
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# Main Goals
This package provides a unified abstract project model for HDL designs and EDA tools.
Third-party frameworks can derive own classes and implement additional logic to create
a concrete project model for their tools.
Frameworks consuming this model can build higher level features and services on top of
such a model, while supporting multiple input sources.
# Data Model
1. The toplevel element is a `Project`, which contains one or multiple designs.
2. A `Design` is a variant of a project and contains filesets.
3. A `FileSet` contains files or further sub-filesets.
4. A `File` represents a single file. E.g. source files, configuration files, constraint files.
5. A `VHDLLibrary` represents a group of `VHDLSourceFile`s being compiled into the same VHDL library.
# Features
* Construct a project model:
* top-down (project → design → fileset → file) or
* bottom-up (file → fileset → design → project) or
* parsing a project file.
* Designs, filesets and files can use absolute or relative paths.
* `ResolvedPath` returns the resolved absolute path to an object.
* Projects, designs, filesets and files can be validated (e.g. if the path exists).
* Projects, designs, filesets and files can have user-defined attributes.
* User-defined attributes are resolved bottom-up.
# Project File Readers
## OSVVM `*.pro` File Reader
ProjectModel can read `*.pro` files and extract source files. Included `*.pro` files
are represented as sub-filesets.
## Xilinx Vivado `*.xpr` Reader
ProjectModel can read `*.xpr` files and extract source, constraint and simulation
files while preserving the fileset structure.
# Use Cases
* Reading OSVVM's `*.pro` files.
* Reading Xilinx Vivado's `*.xpr` files.
# Examples
```python
from pathlib import Path
from pyEDAA.ProjectModel import Project, Design, FileSet, VHDLSourceFile
print(f"Current working directory: {Path.cwd()}")
projectDirectory = Path.cwd() / "../project"
print(f"Project directory: {projectDirectory!s} - {projectDirectory.exists()}")
project = Project("myProject", rootDirectory=projectDirectory)
designA = Design("designA", project=project, directory=Path("designA"))
designAFileset = FileSet("srcA", design=designA)
for vhdlFilePath in designAFileset.ResolvedPath.glob("*.vhdl"):
designAFileset.AddFile(VHDLSourceFile(vhdlFilePath))
libFileset = FileSet("lib", Path("../lib"), design=designA)
for vhdlFilePath in libFileset.ResolvedPath.glob("*.vhdl"):
libFileset.AddFile(VHDLSourceFile(vhdlFilePath))
print(f"All VHDL files in {designA.Name}:")
for file in designA.Files(fileType=VHDLSourceFile):
print(f" {file.Path}")
```
# Consumers
This layer is used by:
* 🚧 pyEDAA.Workflow
# References
* [Paebbels/pyIPCMI: pyIPCMI/Base/Project.py](https://GitHub.com/Paebbels/pyIPCMI/blob/master/pyIPCMI/Base/Project.py)
* [VUnit/vunit: vunit/project.py](https://GitHub.com/VUnit/vunit/blob/master/vunit/project.py)
* [PyFPGA/pyfpga: fpga/project.py](https://GitHub.com/PyFPGA/pyfpga/blob/main/fpga/project.py)
* [olofk/fusesoc: fusesoc/capi2/core.py](https://GitHub.com/olofk/fusesoc/blob/master/fusesoc/capi2/core.py)
* [XedaHQ/xeda: xeda/flows/flow.py](https://GitHub.com/XedaHQ/xeda/blob/master/xeda/flows/flow.py)
* [tsfpga/tsfpga: tsfpga/build_project_list.py](https://gitlab.com/tsfpga/tsfpga/-/blob/master/tsfpga/build_project_list.py)
* [hdl-make: hdlmake/](https://ohwr.org/project/hdl-make/tree/master/hdlmake)
* [OSVVM/OSVVM-Scripts: OsvvmProjectScripts.tcl](https://GitHub.com/OSVVM/OSVVM-Scripts/blob/master/OsvvmProjectScripts.tcl)
# Contributors
* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)
* [Unai Martinez-Corral](https://GitHub.com/umarcor)
* [Stefan Unrein](https://GitHub.com/stefanunrein)
* [and more...](https://GitHub.com/edaa-org/pyEDAA.ProjectModel/graphs/contributors)
# License
This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).
The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).
-------------------------
SPDX-License-Identifier: Apache-2.0
Raw data
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"description": "<p align=\"center\">\n <a title=\"edaa-org.github.io/pySVModel\" href=\"https://edaa-org.github.io/pyEDAA.ProjectModel\"><img height=\"80px\" src=\"doc/_static/logo_on_dark.svg\"/></a>\n</p>\n\n[](https://GitHub.com/edaa-org/pyEDAA.ProjectModel)\n[](LICENSE.md)\n[](https://edaa-org.github.io/pyEDAA.ProjectModel/)\n[](LICENSE.md)\n[](https://gitter.im/hdl/community) \n[](https://pypi.org/project/pyEDAA.ProjectModel/)\n\n \n[](https://GitHub.com/edaa-org/pyEDAA.ProjectModel/actions/workflows/Pipeline.yml)\n[](https://libraries.io/github/edaa-org/pyEDAA.ProjectModel)\n[](https://www.codacy.com/gh/edaa-org/pyEDAA.ProjectModel)\n[](https://www.codacy.com/gh/edaa-org/pyEDAA.ProjectModel)\n[](https://codecov.io/gh/edaa-org/pyEDAA.ProjectModel)\n\n<!--\n[](https://github.com/edaa-org/pyEDAA.ProjectModel/network/dependents)\n[](https://requires.io/github/edaa-org/pyEDAA.ProjectModel/requirements/?branch=main)\n[](https://libraries.io/github/edaa-org/pyEDAA.ProjectModel/sourcerank) \n-->\n\n# Main Goals\n\nThis package provides a unified abstract project model for HDL designs and EDA tools.\nThird-party frameworks can derive own classes and implement additional logic to create\na concrete project model for their tools.\n\nFrameworks consuming this model can build higher level features and services on top of\nsuch a model, while supporting multiple input sources.\n\n# Data Model\n\n1. The toplevel element is a `Project`, which contains one or multiple designs.\n2. A `Design` is a variant of a project and contains filesets.\n3. A `FileSet` contains files or further sub-filesets.\n4. A `File` represents a single file. E.g. source files, configuration files, constraint files.\n5. A `VHDLLibrary` represents a group of `VHDLSourceFile`s being compiled into the same VHDL library.\n\n\n\n# Features\n\n* Construct a project model: \n * top-down (project → design → fileset → file) or\n * bottom-up (file → fileset → design → project) or\n * parsing a project file.\n\n* Designs, filesets and files can use absolute or relative paths.\n * `ResolvedPath` returns the resolved absolute path to an object.\n\n* Projects, designs, filesets and files can be validated (e.g. if the path exists).\n\n* Projects, designs, filesets and files can have user-defined attributes.\n * User-defined attributes are resolved bottom-up.\n\n# Project File Readers\n\n## OSVVM `*.pro` File Reader\n\nProjectModel can read `*.pro` files and extract source files. Included `*.pro` files\nare represented as sub-filesets.\n\n## Xilinx Vivado `*.xpr` Reader\n\nProjectModel can read `*.xpr` files and extract source, constraint and simulation\nfiles while preserving the fileset structure.\n\n# Use Cases\n\n* Reading OSVVM's `*.pro` files.\n* Reading Xilinx Vivado's `*.xpr` files.\n\n# Examples\n\n```python\nfrom pathlib import Path\nfrom pyEDAA.ProjectModel import Project, Design, FileSet, VHDLSourceFile\n\nprint(f\"Current working directory: {Path.cwd()}\")\nprojectDirectory = Path.cwd() / \"../project\"\nprint(f\"Project directory: {projectDirectory!s} - {projectDirectory.exists()}\")\n\nproject = Project(\"myProject\", rootDirectory=projectDirectory)\ndesignA = Design(\"designA\", project=project, directory=Path(\"designA\"))\ndesignAFileset = FileSet(\"srcA\", design=designA)\nfor vhdlFilePath in designAFileset.ResolvedPath.glob(\"*.vhdl\"):\n\tdesignAFileset.AddFile(VHDLSourceFile(vhdlFilePath))\n\nlibFileset = FileSet(\"lib\", Path(\"../lib\"), design=designA)\nfor vhdlFilePath in libFileset.ResolvedPath.glob(\"*.vhdl\"):\n\tlibFileset.AddFile(VHDLSourceFile(vhdlFilePath))\n\nprint(f\"All VHDL files in {designA.Name}:\")\nfor file in designA.Files(fileType=VHDLSourceFile):\n\tprint(f\" {file.Path}\")\n```\n\n# Consumers\n\nThis layer is used by:\n\n* \ud83d\udea7 pyEDAA.Workflow\n\n\n# References\n\n* [Paebbels/pyIPCMI: pyIPCMI/Base/Project.py](https://GitHub.com/Paebbels/pyIPCMI/blob/master/pyIPCMI/Base/Project.py)\n* [VUnit/vunit: vunit/project.py](https://GitHub.com/VUnit/vunit/blob/master/vunit/project.py)\n* [PyFPGA/pyfpga: fpga/project.py](https://GitHub.com/PyFPGA/pyfpga/blob/main/fpga/project.py)\n* [olofk/fusesoc: fusesoc/capi2/core.py](https://GitHub.com/olofk/fusesoc/blob/master/fusesoc/capi2/core.py)\n* [XedaHQ/xeda: xeda/flows/flow.py](https://GitHub.com/XedaHQ/xeda/blob/master/xeda/flows/flow.py)\n* [tsfpga/tsfpga: tsfpga/build_project_list.py](https://gitlab.com/tsfpga/tsfpga/-/blob/master/tsfpga/build_project_list.py)\n* [hdl-make: hdlmake/](https://ohwr.org/project/hdl-make/tree/master/hdlmake)\n* [OSVVM/OSVVM-Scripts: OsvvmProjectScripts.tcl](https://GitHub.com/OSVVM/OSVVM-Scripts/blob/master/OsvvmProjectScripts.tcl)\n\n# Contributors\n\n* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)\n* [Unai Martinez-Corral](https://GitHub.com/umarcor)\n* [Stefan Unrein](https://GitHub.com/stefanunrein)\n* [and more...](https://GitHub.com/edaa-org/pyEDAA.ProjectModel/graphs/contributors)\n\n# License\n\nThis Python package (source code) licensed under [Apache License 2.0](LICENSE.md). \nThe accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).\n\n-------------------------\nSPDX-License-Identifier: Apache-2.0\n",
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