PyVerilator-mm
==============
This is a fork of the original pyverilator package, that manages a newer verilator syntax
and works with WSL (by importing tclwraper only if gtkwave is required).
Below the original readme.
PyVerilator
===========
This package provides a wrapper to generate and use verilator
hardware models in python.
Installing Non-Development Version
----------------------------------
If you want to just install the `pyverilator` package, you should be able to
using the following command:
$ pip3 install pyverilator
Installing Development Version
-------------------------------
pip3 install git+https://github.com/bat52/pyverilator.git@master
Usage
-----
Assume you have the following verilog module stored in ``counter.v``.
.. code:: verilog
module counter (
input clk,
input rst,
input en,
output [7:0] out
);
reg [7:0] count_reg;
wire [7:0] next_count_reg;
assign next_count_reg = (en == 1) ? count_reg + 1 : count_reg;
assign out = next_count_reg;
always @(posedge clk) begin
if (rst == 1) count_reg <= 0;
else count_reg <= next_count_reg;
end
endmodule
Then you can use ``pyverilator`` to simulate this module using verilator in
python.
.. code:: python
sim = pyverilator.PyVerilator.build('counter.v')
# start gtkwave to view the waveforms as they are made
sim.start_gtkwave()
# add all the io and internal signals to gtkwave
sim.send_signals_to_gtkwave(sim.io)
# sim.send_signals_to_gtkwave(sim.internals) # not working anymore
# add all the io and internal signals to gtkwave
sim.send_to_gtkwave(sim.io)
# sim.send_to_gtkwave(sim.internals) # not working anymore
# tick the automatically detected clock
sim.clock.tick()
# set rst back to 0
sim.io.rst = 0
# check out when en = 0
sim.io.en = 0
curr_out = sim.io.out
# sim.io is a pyverilator.Collection, accessing signals by attribute or
# dictionary syntax returns a SignalValue object which inherits from int.
# sim.io.out can be used just like an int in most cases, and it has extra
# features like being able to add it to gtkwave with
# sim.io.out.send_to_gtkwave(). To just get the int value, you can call
# sim.io.out.value
print('sim.io.out = ' + str(curr_out))
# check out when en = 1
sim.io.en = 1
curr_out = sim.io.out
print('sim.io.out = ' + str(curr_out))
sim.clock.tick()
# check out after ticking clock
curr_out = sim.io.out
print('sim.io.out = ' + str(curr_out))
The full code for this and other examples can be found in the examples folder
of the git repository.
Installing for Development
--------------------------
To install this package for development, you should use a virtual environment,
and install the package in editable mode using pip.
To create a virtual environment for this project, run the command below.
$ python3 -m venv path/to/new-venv-folder
To start using your new virtual environment, run the command below.
This needs to be run each time you open a new terminal.
$ source path/to/new-venv-folder/bin/activate
At this point you are now using your new virtual environment.
Python packages you install in this environment will not be available outside
your virtual environment.
If you want to stop using the virtual environment, just run ``deactivate``.
To install the ``pyverilator`` package in editable mode, inside the
``pyverilator`` top git repository folder, run the command below.
$ pip3 install -e .
Raw data
{
"_id": null,
"home_page": "https://github.com/bat52/pyverilator",
"name": "pyverilator-mm",
"maintainer": "",
"docs_url": null,
"requires_python": "",
"maintainer_email": "",
"keywords": "Verilator Wrapper Verilog",
"author": "CSAIL CSG, Marco Merlin",
"author_email": "acwright@mit.edu, bthom@mit.edu",
"download_url": "https://files.pythonhosted.org/packages/8a/1b/e97ff598ed52e062f2bf1c7209c73539c2a76480626caa2bf222b5cd09d4/pyverilator-mm-0.7.6.tar.gz",
"platform": null,
"description": "PyVerilator-mm\n==============\n\nThis is a fork of the original pyverilator package, that manages a newer verilator syntax \nand works with WSL (by importing tclwraper only if gtkwave is required).\nBelow the original readme.\n\nPyVerilator\n===========\n\nThis package provides a wrapper to generate and use verilator\nhardware models in python.\n\n\nInstalling Non-Development Version\n----------------------------------\n\nIf you want to just install the `pyverilator` package, you should be able to\nusing the following command:\n\n\n $ pip3 install pyverilator\n\nInstalling Development Version\n-------------------------------\n\n pip3 install git+https://github.com/bat52/pyverilator.git@master\n\nUsage\n-----\n\nAssume you have the following verilog module stored in ``counter.v``.\n\n.. code:: verilog\n\n module counter (\n input clk,\n input rst,\n input en,\n output [7:0] out\n );\n reg [7:0] count_reg;\n wire [7:0] next_count_reg;\n assign next_count_reg = (en == 1) ? count_reg + 1 : count_reg;\n assign out = next_count_reg;\n always @(posedge clk) begin\n if (rst == 1) count_reg <= 0;\n else count_reg <= next_count_reg;\n end\n endmodule\n\nThen you can use ``pyverilator`` to simulate this module using verilator in\npython.\n\n.. code:: python\n\n sim = pyverilator.PyVerilator.build('counter.v')\n\n # start gtkwave to view the waveforms as they are made\n sim.start_gtkwave()\n\n # add all the io and internal signals to gtkwave\n sim.send_signals_to_gtkwave(sim.io)\n # sim.send_signals_to_gtkwave(sim.internals) # not working anymore\n\n # add all the io and internal signals to gtkwave\n sim.send_to_gtkwave(sim.io)\n # sim.send_to_gtkwave(sim.internals) # not working anymore\n\n # tick the automatically detected clock\n sim.clock.tick()\n\n # set rst back to 0\n sim.io.rst = 0\n\n # check out when en = 0\n sim.io.en = 0\n curr_out = sim.io.out\n # sim.io is a pyverilator.Collection, accessing signals by attribute or\n # dictionary syntax returns a SignalValue object which inherits from int.\n # sim.io.out can be used just like an int in most cases, and it has extra\n # features like being able to add it to gtkwave with\n # sim.io.out.send_to_gtkwave(). To just get the int value, you can call\n # sim.io.out.value\n print('sim.io.out = ' + str(curr_out))\n\n # check out when en = 1\n sim.io.en = 1\n curr_out = sim.io.out\n print('sim.io.out = ' + str(curr_out))\n\n sim.clock.tick()\n\n # check out after ticking clock\n curr_out = sim.io.out\n print('sim.io.out = ' + str(curr_out))\n\nThe full code for this and other examples can be found in the examples folder\nof the git repository.\n\nInstalling for Development\n--------------------------\n\nTo install this package for development, you should use a virtual environment,\nand install the package in editable mode using pip.\n\nTo create a virtual environment for this project, run the command below.\n\n $ python3 -m venv path/to/new-venv-folder\n\nTo start using your new virtual environment, run the command below.\nThis needs to be run each time you open a new terminal.\n\n $ source path/to/new-venv-folder/bin/activate\n\nAt this point you are now using your new virtual environment.\nPython packages you install in this environment will not be available outside\nyour virtual environment.\nIf you want to stop using the virtual environment, just run ``deactivate``.\n\nTo install the ``pyverilator`` package in editable mode, inside the\n``pyverilator`` top git repository folder, run the command below.\n\n $ pip3 install -e .\n\n\n",
"bugtrack_url": null,
"license": "",
"summary": "Python interface to Verilator models",
"version": "0.7.6",
"project_urls": {
"Bug Reports": "https://github.com/bat52/pyverilator/issues",
"Homepage": "https://github.com/bat52/pyverilator",
"Source": "https://github.com/bat52/pyverilator"
},
"split_keywords": [
"verilator",
"wrapper",
"verilog"
],
"urls": [
{
"comment_text": "",
"digests": {
"blake2b_256": "8a1be97ff598ed52e062f2bf1c7209c73539c2a76480626caa2bf222b5cd09d4",
"md5": "d7e2e337fa1b208402fbf2a359d0d3c3",
"sha256": "ac5b91a355cabd1f1f0830fe573be00616c8220f4c49120ef25c17530ed4d786"
},
"downloads": -1,
"filename": "pyverilator-mm-0.7.6.tar.gz",
"has_sig": false,
"md5_digest": "d7e2e337fa1b208402fbf2a359d0d3c3",
"packagetype": "sdist",
"python_version": "source",
"requires_python": null,
"size": 17258,
"upload_time": "2024-01-21T11:25:40",
"upload_time_iso_8601": "2024-01-21T11:25:40.727364Z",
"url": "https://files.pythonhosted.org/packages/8a/1b/e97ff598ed52e062f2bf1c7209c73539c2a76480626caa2bf222b5cd09d4/pyverilator-mm-0.7.6.tar.gz",
"yanked": false,
"yanked_reason": null
}
],
"upload_time": "2024-01-21 11:25:40",
"github": true,
"gitlab": false,
"bitbucket": false,
"codeberg": false,
"github_user": "bat52",
"github_project": "pyverilator",
"travis_ci": false,
"coveralls": false,
"github_actions": false,
"requirements": [],
"lcname": "pyverilator-mm"
}
JSON
