| Name | ruapu JSON |
| Version |
0.1.0
JSON |
| download |
| home_page | |
| Summary | The Python binding of ruapu. |
| upload_time | 2024-02-27 13:33:00 |
| maintainer | |
| docs_url | None |
| author | |
| requires_python | >=3.5 |
| license | MIT |
| keywords |
ruapu
cpu
isa
detect
|
| VCS |
 |
| bugtrack_url |
|
| requirements |
No requirements were recorded.
|
| Travis-CI |
|
| coveralls test coverage |
No coveralls.
|
# ruapu
Detect CPU ISA features with single-file
<table>
<tr><td>CPU</td><td>✅ x86, x86-64<br/>✅ arm, aarch64<br/>✅ mips<br/>✅ powerpc<br/>✅ s390x<br/>✅ loongarch<br/>✅ risc-v<br/>✅ openrisc</td><td rowspan=3>
```c
#define RUAPU_IMPLEMENTATION
#include "ruapu.h"
int main()
{
// initialize ruapu once
ruapu_init();
// now, tell me if this cpu has avx2
int has_avx2 = ruapu_supports("avx2");
return 0;
}
```
</td></tr>
<tr><td>OS</td><td>✅ Windows<br/>✅ Linux<br/>✅ macOS<br/>✅ Android<br/>✅ iOS<br/>✅ FreeBSD<br/>✅ NetBSD<br/>✅ OpenBSD</td></tr>
<tr><td>Compiler</td><td>✅ GCC<br/>✅ Clang<br/>✅ MSVC<br/>✅ MinGW</td></tr>
</table>
#### Best practice for using `ruapu.h` in multiple compilation units
1. Create one `ruapu.c` for your project
2. `ruapu.c` is **ONLY** `#define RUAPU_IMPLEMENTATION` and `#include "ruapu.h"`
3. Other sources `#include "ruapu.h"` but **NO** `#define RUAPU_IMPLEMENTATION`
## Let's ruapu
### ruapu with C
<table>
<tr><td>
Compile ruapu test program
```shell
# GCC / MinGW
gcc main.c -o ruapu
```
```shell
# Clang
clang main.c -o ruapu
```
```shell
# MSVC
cl.exe /Fe: ruapu.exe main.c
```
</td>
<td>
Run ruapu in command line
```shell
./ruapu
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
... more lines omitted ...
```
</td></tr>
</table>
### ruapu with Python
<table>
<tr><td>
Compile and install ruapu library
```shell
# from source code
pip3 install .
```
</td>
<td>
Use ruapu in python
```python
import ruapu
ruapu.supports("avx2")
# True
ruapu.supports(isa="avx2")
# True
```
</td></tr>
</table>
<details>
<summary>Github-hosted runner result (Linux)</summary>
```
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
```
</details>
<details>
<summary>Github-hosted runner result (macOS)</summary>
```
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 0
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
```
</details>
<details>
<summary>Github-hosted runner result (macOS M1)</summary>
```
neon = 1
vfpv4 = 1
cpuid = 0
asimdhp = 1
asimddp = 1
asimdfhm = 1
bf16 = 0
i8mm = 0
sve = 0
sve2 = 0
svebf16 = 0
svei8mm = 0
svef32mm = 0
```
</details>
<details>
<summary>Github-hosted runner result (Windows)</summary>
```
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
```
</details>
<details>
<summary>FreeBSD/NetBSD/OpenBSD VM result (x86_64)</summary>
```
mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
fma4 = 0
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0
```
</details>
## Features
* Detect **CPU ISA with single-file**   
_`sse2`, `avx`, `avx512f`, `neon`, etc._
* Detect **vendor extended ISA**    
_apple `amx`, risc-v vendor ISA, etc._
* Detect **richer ISA on Windows ARM**  
_`IsProcessorFeaturePresent()` returns little ISA information_
* Detect **`x86-avx512` on macOS correctly** 
_macOS hides it in `cpuid`_
* Detect **new CPU's ISA on old systems** 
_they are usually not exposed in `auxv` or `MISA`_
* Detect **CPU hidden ISA**       
_`fma4` on zen1, ISA in hypervisor, etc._
## Supported ISA _ (more is comming ... :)_
|CPU|ISA|
|:---:|---|
|x86|`mmx` `sse` `sse2` `sse3` `ssse3` `sse41` `sse42` `sse4a` `xop` `avx` `f16c` `fma` `fma4` `avx2` `avx512f` `avx512bw` `avx512cd` `avx512dq` `avx512vl` `avx512vnni` `avx512bf16` `avx512ifma` `avx512vbmi` `avx512vbmi2` `avx512fp16` `avxvnni` `avxvnniint8` `avxifma`|
|arm|`edsp` `neon` `vfpv4` `idiv`|
|aarch64|`neon` `vfpv4` `cpuid` `asimdrdm` `asimdhp` `asimddp` `asimdfhm` `bf16` `i8mm` `mte` `sve` `sve2` `svebf16` `svei8mm` `svef32mm` `pmull` `crc32` `aes` `sha1` `sha2` `sha3` `sha512` `sm3` `sm4` `amx`|
|mips|`msa`|
|powerpc|`vsx`|
|s390x|`zvector`|
|loongarch|`lsx` `lasx`|
|risc-v|`i` `m` `a` `f` `d` `c` `zfa` `zfh` `zfhmin` `zicsr` `zifencei` `zmmul` |
|openrisc| `orbis32` `orbis64` `orfpx32` `orfpx64` `orvdx64` |
## Techniques inside ruapu
ruapu is implemented in C language to ensure the widest possible portability.
ruapu determines whether the CPU supports certain instruction sets by trying to execute instructions and detecting whether an `Illegal Instruction` exception occurs. ruapu does not rely on the cpuid instructions and registers related to the CPU architecture, nor does it rely on the `MISA` information and system calls of the operating system. This can help us get more detailed CPU ISA information.
## FAQ
#### Why is the project named ruapu
 ruapu is the abbreviation of rua-cpu, which means using various extended instructions to harass and amuse the CPU (rua!). Based on whether the CPU reacts violently (throws an illegal instruction exception), it is inferred whether the CPU supports a certain extended instruction set.
#### Why is ruapu API designed like this
 We consider gcc builtin functions to be good practice, saying `__builtin_cpu_init()` and `__builtin_cpu_supports()`. ruapu refers to this design, which can be a 1:1 replacement for gcc functions, and supports more operating systems and compilers, giving it better portability.
#### Why does SIGILL occur when executing in debugger or simulator, such as `gdb`, `lldb`, `qemu-user`, `sde` etc.
 Because debuggers and simulators capture the signal and stop the ruapu signal handler function by default, we can continue execution at this time, or configure it specifically, such as `handle SIGILL nostop` in gdb. ruapu technically cannot prevent programs from stopping in debuggers and emulators
#### How to add detection capabilities for new instructions to ruapu
 _Assume that the new extended instruction set is named `rua`_
1. Add `RUAPU_INSTCODE(rua, rua-inst-hex) // rua r0,r0` and `RUAPU_ISAENTRY(rua)` in `ruapu.h`
2. Add `PRINT_ISA_SUPPORT(rua)` in `main.c` to print the detection result
3. Add entries about `rua` in README.md
4. Create a pull request!
 _https://godbolt.org/ is a good helper to view the compiled binary code of instructions._
## Repos that use ruapu
* [ncnn](https://github.com/Tencent/ncnn)  _High-performance neural network inference framework_
* [libllm](https://github.com/ling0322/libllm)  _Efficient inference of large language models_
## Credits
* [@nihui](https://github.com/nihui)  _Write the initial POC code and ruapu maintainer_
* [@kernelbin](https://github.com/kernelbin)  _Implement exception handling for Windows_
* [@zchrissirhcz](https://github.com/zchrissirhcz)  _Detect x86 FMA4_
* [@MollySophia](https://github.com/MollySophia)  _Fix C++ export symbol_
* [@strongtz](https://github.com/strongtz)  _Detect more aarch64 ISA_
* [@monkeyking](https://github.com/monkeyking)  _Detect apple arm64 AMX_
* [@junchao-loongson](https://github.com/junchao-loongson)  _Add loongarch support_
* [@ziyao233](https://github.com/ziyao233)  _Detect more risc-v ISA_
* [@dreamcmi](https://github.com/dreamcmi)  _Detect more risc-v ISA_
* [@cocoa-xu](https://github.com/cocoa-xu)  _Add FreeBSD support, python support_
* [@YuzukiTsuru](https://github.com/YuzukiTsuru)  _Add OpenRISC support_
## License
MIT License
Raw data
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"description": "# ruapu\n\n\n\n\nDetect CPU ISA features with single-file\n\n<table>\n<tr><td>CPU</td><td>✅ x86, x86-64<br/>✅ arm, aarch64<br/>✅ mips<br/>✅ powerpc<br/>✅ s390x<br/>✅ loongarch<br/>✅ risc-v<br/>✅ openrisc</td><td rowspan=3>\n \n```c\n#define RUAPU_IMPLEMENTATION\n#include \"ruapu.h\"\n\nint main()\n{\n // initialize ruapu once\n ruapu_init();\n\n // now, tell me if this cpu has avx2\n int has_avx2 = ruapu_supports(\"avx2\");\n\n return 0;\n}\n```\n\n</td></tr>\n<tr><td>OS</td><td>✅ Windows<br/>✅ Linux<br/>✅ macOS<br/>✅ Android<br/>✅ iOS<br/>✅ FreeBSD<br/>✅ NetBSD<br/>✅ OpenBSD</td></tr>\n<tr><td>Compiler</td><td>✅ GCC<br/>✅ Clang<br/>✅ MSVC<br/>✅ MinGW</td></tr>\n</table>\n\n#### Best practice for using `ruapu.h` in multiple compilation units\n\n1. Create one `ruapu.c` for your project\n2. `ruapu.c` is **ONLY** `#define RUAPU_IMPLEMENTATION` and `#include \"ruapu.h\"`\n3. Other sources `#include \"ruapu.h\"` but **NO** `#define RUAPU_IMPLEMENTATION`\n\n## Let's ruapu\n\n### ruapu with C\n\n<table>\n\n<tr><td>\n\nCompile ruapu test program\n\n```shell\n# GCC / MinGW\ngcc main.c -o ruapu\n```\n```shell\n# Clang\nclang main.c -o ruapu\n```\n```shell\n# MSVC\ncl.exe /Fe: ruapu.exe main.c\n```\n</td>\n<td>\n\nRun ruapu in command line\n\n```shell\n./ruapu \nmmx = 1\nsse = 1\nsse2 = 1\nsse3 = 1\nssse3 = 1\nsse41 = 1\nsse42 = 1\nsse4a = 1\nxop = 0\n... more lines omitted ...\n```\n\n</td></tr>\n</table>\n\n### ruapu with Python\n\n<table>\n\n<tr><td>\n\nCompile and install ruapu library\n\n```shell\n# from source code\npip3 install .\n```\n</td>\n<td>\n\nUse ruapu in python\n\n```python\nimport ruapu\n\nruapu.supports(\"avx2\")\n# True\n\nruapu.supports(isa=\"avx2\")\n# True\n```\n</td></tr>\n</table>\n\n<details>\n<summary>Github-hosted runner result (Linux)</summary>\n\n```\nmmx = 1\nsse = 1\nsse2 = 1\nsse3 = 1\nssse3 = 1\nsse41 = 1\nsse42 = 1\nsse4a = 1\nxop = 0\navx = 1\nf16c = 1\nfma = 1\navx2 = 1\navx512f = 0\navx512bw = 0\navx512cd = 0\navx512dq = 0\navx512vl = 0\navx512vnni = 0\navx512bf16 = 0\navx512ifma = 0\navx512vbmi = 0\navx512vbmi2 = 0\navx512fp16 = 0\navxvnni = 0\navxvnniint8 = 0\navxifma = 0\n```\n\n</details>\n\n<details>\n<summary>Github-hosted runner result (macOS)</summary>\n\n```\nmmx = 1\nsse = 1\nsse2 = 1\nsse3 = 1\nssse3 = 1\nsse41 = 1\nsse42 = 1\nsse4a = 0\nxop = 0\navx = 1\nf16c = 1\nfma = 1\navx2 = 1\navx512f = 0\navx512bw = 0\navx512cd = 0\navx512dq = 0\navx512vl = 0\navx512vnni = 0\navx512bf16 = 0\navx512ifma = 0\navx512vbmi = 0\navx512vbmi2 = 0\navx512fp16 = 0\navxvnni = 0\navxvnniint8 = 0\navxifma = 0\n```\n\n</details>\n\n<details>\n<summary>Github-hosted runner result (macOS M1)</summary>\n\n```\nneon = 1\nvfpv4 = 1\ncpuid = 0\nasimdhp = 1\nasimddp = 1\nasimdfhm = 1\nbf16 = 0\ni8mm = 0\nsve = 0\nsve2 = 0\nsvebf16 = 0\nsvei8mm = 0\nsvef32mm = 0\n```\n\n</details>\n\n<details>\n<summary>Github-hosted runner result (Windows)</summary>\n\n```\nmmx = 1\nsse = 1\nsse2 = 1\nsse3 = 1\nssse3 = 1\nsse41 = 1\nsse42 = 1\nsse4a = 1\nxop = 0\navx = 1\nf16c = 1\nfma = 1\navx2 = 1\navx512f = 0\navx512bw = 0\navx512cd = 0\navx512dq = 0\navx512vl = 0\navx512vnni = 0\navx512bf16 = 0\navx512ifma = 0\navx512vbmi = 0\navx512vbmi2 = 0\navx512fp16 = 0\navxvnni = 0\navxvnniint8 = 0\navxifma = 0\n```\n\n</details>\n\n<details>\n<summary>FreeBSD/NetBSD/OpenBSD VM result (x86_64)</summary>\n\n```\nmmx = 1\nsse = 1\nsse2 = 1\nsse3 = 1\nssse3 = 1\nsse41 = 1\nsse42 = 1\nsse4a = 1\nxop = 0\navx = 1\nf16c = 1\nfma = 1\nfma4 = 0\navx2 = 1\navx512f = 0\navx512bw = 0\navx512cd = 0\navx512dq = 0\navx512vl = 0\navx512vnni = 0\navx512bf16 = 0\navx512ifma = 0\navx512vbmi = 0\navx512vbmi2 = 0\navx512fp16 = 0\navxvnni = 0\navxvnniint8 = 0\navxifma = 0\n```\n\n</details>\n\n\n## Features\n\n* Detect **CPU ISA with single-file**   \n_`sse2`, `avx`, `avx512f`, `neon`, etc._\n* Detect **vendor extended ISA**    \n_apple `amx`, risc-v vendor ISA, etc._\n* Detect **richer ISA on Windows ARM**  \n_`IsProcessorFeaturePresent()` returns little ISA information_\n* Detect **`x86-avx512` on macOS correctly** \n_macOS hides it in `cpuid`_\n* Detect **new CPU's ISA on old systems** \n_they are usually not exposed in `auxv` or `MISA`_\n* Detect **CPU hidden ISA**       \n_`fma4` on zen1, ISA in hypervisor, etc._\n\n## Supported ISA _ (more is comming ... :)_\n\n|CPU|ISA|\n|:---:|---|\n|x86|`mmx` `sse` `sse2` `sse3` `ssse3` `sse41` `sse42` `sse4a` `xop` `avx` `f16c` `fma` `fma4` `avx2` `avx512f` `avx512bw` `avx512cd` `avx512dq` `avx512vl` `avx512vnni` `avx512bf16` `avx512ifma` `avx512vbmi` `avx512vbmi2` `avx512fp16` `avxvnni` `avxvnniint8` `avxifma`|\n|arm|`edsp` `neon` `vfpv4` `idiv`|\n|aarch64|`neon` `vfpv4` `cpuid` `asimdrdm` `asimdhp` `asimddp` `asimdfhm` `bf16` `i8mm` `mte` `sve` `sve2` `svebf16` `svei8mm` `svef32mm` `pmull` `crc32` `aes` `sha1` `sha2` `sha3` `sha512` `sm3` `sm4` `amx`|\n|mips|`msa`|\n|powerpc|`vsx`|\n|s390x|`zvector`|\n|loongarch|`lsx` `lasx`|\n|risc-v|`i` `m` `a` `f` `d` `c` `zfa` `zfh` `zfhmin` `zicsr` `zifencei` `zmmul` |\n|openrisc| `orbis32` `orbis64` `orfpx32` `orfpx64` `orvdx64` |\n\n## Techniques inside ruapu\nruapu is implemented in C language to ensure the widest possible portability.\n\nruapu determines whether the CPU supports certain instruction sets by trying to execute instructions and detecting whether an `Illegal Instruction` exception occurs. ruapu does not rely on the cpuid instructions and registers related to the CPU architecture, nor does it rely on the `MISA` information and system calls of the operating system. This can help us get more detailed CPU ISA information.\n\n## FAQ\n#### Why is the project named ruapu\n\n ruapu is the abbreviation of rua-cpu, which means using various extended instructions to harass and amuse the CPU (rua!). Based on whether the CPU reacts violently (throws an illegal instruction exception), it is inferred whether the CPU supports a certain extended instruction set.\n\n#### Why is ruapu API designed like this\n\n We consider gcc builtin functions to be good practice, saying `__builtin_cpu_init()` and `__builtin_cpu_supports()`. ruapu refers to this design, which can be a 1:1 replacement for gcc functions, and supports more operating systems and compilers, giving it better portability.\n\n#### Why does SIGILL occur when executing in debugger or simulator, such as `gdb`, `lldb`, `qemu-user`, `sde` etc.\n\n Because debuggers and simulators capture the signal and stop the ruapu signal handler function by default, we can continue execution at this time, or configure it specifically, such as `handle SIGILL nostop` in gdb. ruapu technically cannot prevent programs from stopping in debuggers and emulators\n\n#### How to add detection capabilities for new instructions to ruapu\n\n _Assume that the new extended instruction set is named `rua`_\n\n1. Add `RUAPU_INSTCODE(rua, rua-inst-hex) // rua r0,r0` and `RUAPU_ISAENTRY(rua)` in `ruapu.h`\n2. Add `PRINT_ISA_SUPPORT(rua)` in `main.c` to print the detection result\n3. Add entries about `rua` in README.md\n4. Create a pull request!\n\n _https://godbolt.org/ is a good helper to view the compiled binary code of instructions._\n\n## Repos that use ruapu\n* [ncnn](https://github.com/Tencent/ncnn)  _High-performance neural network inference framework_\n* [libllm](https://github.com/ling0322/libllm)  _Efficient inference of large language models_\n\n## Credits\n* [@nihui](https://github.com/nihui)  _Write the initial POC code and ruapu maintainer_\n* [@kernelbin](https://github.com/kernelbin)  _Implement exception handling for Windows_\n* [@zchrissirhcz](https://github.com/zchrissirhcz)  _Detect x86 FMA4_\n* [@MollySophia](https://github.com/MollySophia)  _Fix C++ export symbol_\n* [@strongtz](https://github.com/strongtz)  _Detect more aarch64 ISA_\n* [@monkeyking](https://github.com/monkeyking)  _Detect apple arm64 AMX_\n* [@junchao-loongson](https://github.com/junchao-loongson)  _Add loongarch support_\n* [@ziyao233](https://github.com/ziyao233)  _Detect more risc-v ISA_\n* [@dreamcmi](https://github.com/dreamcmi)  _Detect more risc-v ISA_\n* [@cocoa-xu](https://github.com/cocoa-xu)  _Add FreeBSD support, python support_\n* [@YuzukiTsuru](https://github.com/YuzukiTsuru)  _Add OpenRISC support_\n\n## License\nMIT License\n",
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