skidl


Nameskidl JSON
Version 0.0.9 PyPI version JSON
home_pagehttps://github.com/xesscorp/skidl
SummaryA Python package for textually describing electronic circuit schematics.
upload_time2017-02-17 01:15:12
maintainerNone
docs_urlNone
authorXESS Corp.
requires_pythonNone
licenseMIT
keywords skidl electronic circuit schematics
VCS
bugtrack_url
requirements None
Travis-CI
Coveralis test coverage No Coveralis.
            ===============================
skidl
===============================

.. .. image:: https://img.shields.io/travis/xesscorp/skidl.svg
        :target: https://travis-ci.org/xesscorp/skidl

.. image:: https://img.shields.io/pypi/v/skidl.svg
        :target: https://pypi.python.org/pypi/skidl


SKiDL is a module that allows you to compactly describe the interconnection of 
electronic circuits and components using Python.
The resulting Python program performs electrical rules checking
for common mistakes and outputs a netlist that serves as input to
a PCB layout tool.

* Free software: MIT license
* Documentation: http://xesscorp.github.io/skidl

Features
--------

* Has a powerful, flexible syntax (because it *is* Python).
* Permits compact descriptions of electronic circuits (think about *not* tracing
  signals through a multi-page schematic).
* Allows textual descriptions of electronic circuits (think about using 
  ``diff`` and `git <https://en.wikipedia.org/wiki/Git_(software)>`_ for circuits).
* Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).
* Supports linear / hierarchical / mixed descriptions of electronic designs.
* Fosters design reuse (think about using `PyPi <https://pypi.org/>`_ and `Github <https://github.com/>`_
  to distribute electronic designs).
* Makes possible the creation of *smart circuit modules* whose behavior / structure are changed parametrically
  (think about filters whose component values are automatically adjusted based on your
  desired cutoff frequency).
* Can work with any ECAD tool (only two methods are needed: one for reading the part libraries and another
  for outputing the correct netlist format).
* Takes advantage of all the benefits of the Python ecosystem (because it *is* Python).

As a very simple example, the SKiDL program below describes a circuit that
takes an input voltage, divides it by three, and outputs it::

    from skidl import *

    gnd = Net('GND')  # Ground reference.
    vin = Net('VI')   # Input voltage to the divider.
    vout = Net('VO')  # Output voltage from the divider.
    r1, r2 = 2 * Part('device', 'R', TEMPLATE)  # Create two resistors.
    r1.value, r1.footprint = '1K',  'Resistors_SMD:R_0805'  # Set resistor values
    r2.value, r2.footprint = '500', 'Resistors_SMD:R_0805'  # and footprints.
    r1[1] += vin      # Connect the input to the first resistor.
    r2[2] += gnd      # Connect the second resistor to ground.
    vout += r1[2], r2[1]  # Output comes from the connection of the two resistors.

    generate_netlist()

And this is the output that can be fed to a program like KiCad's ``PCBNEW`` to
create the physical PCB::

    (export (version D)
      (design
        (source "C:/Users/DEVB/PycharmProjects/test1\test.py")
        (date "08/12/2016 11:13 AM")
        (tool "SKiDL (0.0.1)"))
      (components
        (comp (ref R1)
          (value 1K)
          (footprint Resistors_SMD:R_0805))
        (comp (ref R2)
          (value 500)
          (footprint Resistors_SMD:R_0805)))
      (nets
        (net (code 0) (name "VI")
          (node (ref R1) (pin 1)))
        (net (code 1) (name "GND")
          (node (ref R2) (pin 2)))
        (net (code 2) (name "VO")
          (node (ref R1) (pin 2))
          (node (ref R2) (pin 1))))
    )




History
-------


0.0.9 (2017-02-16)
______________________

* Use getattr() instead of __class__.__dict__ so that subclasses of SKiDL objects
  can find attributes named within strings without searching the __mor__.


0.0.8 (2017-01-11)
______________________

* skidl_to_netlist now uses templates.
* Default operation of search() is now less exacting.
* Traceback is now suppressed if show() is passed a part name not in a library.


0.0.7 (2016-09-11)
______________________

* Lack of KISYSMOD environment variable no longer causes an exception.
* requirements.txt file now references the requirements from setup.py.
* Changed setup so it generates a pckg_info file with version, author, email.


0.0.6 (2016-09-10)
______________________

* Fixed error caused when trying to find script name when SKiDL is run in interactive mode.
* Silenced errors/warnings when loading KiCad part description (.dcm) files.


0.0.5 (2016-09-07)
______________________

* SKiDL now searches for parts with a user-configurable list of library search paths.
* Part descriptions and keywords are now loaded from the .dcm file associated with a .lib file.


0.0.4 (2016-08-27)
______________________

* SKiDL scripts can now output netlists in XML format.


0.0.3 (2016-08-25)
______________________

* Added command-line utility to convert netlists into SKiDL programs.


0.0.2 (2016-08-17)
______________________

* Changed the link to the documentation.


0.0.1 (2016-08-16)
______________________

* First release on PyPI.
            

Raw data

            {
    "maintainer": null, 
    "docs_url": null, 
    "requires_python": null, 
    "maintainer_email": null, 
    "cheesecake_code_kwalitee_id": null, 
    "coveralis": false, 
    "keywords": "skidl electronic circuit schematics", 
    "tox": true, 
    "requirements": [
        {
            "name": null, 
            "specs": []
        }
    ], 
    "author": "XESS Corp.", 
    "home_page": "https://github.com/xesscorp/skidl", 
    "github_user": "xesscorp", 
    "download_url": "https://pypi.python.org/packages/77/32/344998a91166884448554521633a3ab373a01ae303c06d1c51c31defb0c6/skidl-0.0.9.zip", 
    "platform": "UNKNOWN", 
    "version": "0.0.9", 
    "cheesecake_documentation_id": null, 
    "description": "===============================\nskidl\n===============================\n\n.. .. image:: https://img.shields.io/travis/xesscorp/skidl.svg\n        :target: https://travis-ci.org/xesscorp/skidl\n\n.. image:: https://img.shields.io/pypi/v/skidl.svg\n        :target: https://pypi.python.org/pypi/skidl\n\n\nSKiDL is a module that allows you to compactly describe the interconnection of \nelectronic circuits and components using Python.\nThe resulting Python program performs electrical rules checking\nfor common mistakes and outputs a netlist that serves as input to\na PCB layout tool.\n\n* Free software: MIT license\n* Documentation: http://xesscorp.github.io/skidl\n\nFeatures\n--------\n\n* Has a powerful, flexible syntax (because it *is* Python).\n* Permits compact descriptions of electronic circuits (think about *not* tracing\n  signals through a multi-page schematic).\n* Allows textual descriptions of electronic circuits (think about using \n  ``diff`` and `git <https://en.wikipedia.org/wiki/Git_(software)>`_ for circuits).\n* Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).\n* Supports linear / hierarchical / mixed descriptions of electronic designs.\n* Fosters design reuse (think about using `PyPi <https://pypi.org/>`_ and `Github <https://github.com/>`_\n  to distribute electronic designs).\n* Makes possible the creation of *smart circuit modules* whose behavior / structure are changed parametrically\n  (think about filters whose component values are automatically adjusted based on your\n  desired cutoff frequency).\n* Can work with any ECAD tool (only two methods are needed: one for reading the part libraries and another\n  for outputing the correct netlist format).\n* Takes advantage of all the benefits of the Python ecosystem (because it *is* Python).\n\nAs a very simple example, the SKiDL program below describes a circuit that\ntakes an input voltage, divides it by three, and outputs it::\n\n    from skidl import *\n\n    gnd = Net('GND')  # Ground reference.\n    vin = Net('VI')   # Input voltage to the divider.\n    vout = Net('VO')  # Output voltage from the divider.\n    r1, r2 = 2 * Part('device', 'R', TEMPLATE)  # Create two resistors.\n    r1.value, r1.footprint = '1K',  'Resistors_SMD:R_0805'  # Set resistor values\n    r2.value, r2.footprint = '500', 'Resistors_SMD:R_0805'  # and footprints.\n    r1[1] += vin      # Connect the input to the first resistor.\n    r2[2] += gnd      # Connect the second resistor to ground.\n    vout += r1[2], r2[1]  # Output comes from the connection of the two resistors.\n\n    generate_netlist()\n\nAnd this is the output that can be fed to a program like KiCad's ``PCBNEW`` to\ncreate the physical PCB::\n\n    (export (version D)\n      (design\n        (source \"C:/Users/DEVB/PycharmProjects/test1\\test.py\")\n        (date \"08/12/2016 11:13 AM\")\n        (tool \"SKiDL (0.0.1)\"))\n      (components\n        (comp (ref R1)\n          (value 1K)\n          (footprint Resistors_SMD:R_0805))\n        (comp (ref R2)\n          (value 500)\n          (footprint Resistors_SMD:R_0805)))\n      (nets\n        (net (code 0) (name \"VI\")\n          (node (ref R1) (pin 1)))\n        (net (code 1) (name \"GND\")\n          (node (ref R2) (pin 2)))\n        (net (code 2) (name \"VO\")\n          (node (ref R1) (pin 2))\n          (node (ref R2) (pin 1))))\n    )\n\n\n\n\nHistory\n-------\n\n\n0.0.9 (2017-02-16)\n______________________\n\n* Use getattr() instead of __class__.__dict__ so that subclasses of SKiDL objects\n  can find attributes named within strings without searching the __mor__.\n\n\n0.0.8 (2017-01-11)\n______________________\n\n* skidl_to_netlist now uses templates.\n* Default operation of search() is now less exacting.\n* Traceback is now suppressed if show() is passed a part name not in a library.\n\n\n0.0.7 (2016-09-11)\n______________________\n\n* Lack of KISYSMOD environment variable no longer causes an exception.\n* requirements.txt file now references the requirements from setup.py.\n* Changed setup so it generates a pckg_info file with version, author, email.\n\n\n0.0.6 (2016-09-10)\n______________________\n\n* Fixed error caused when trying to find script name when SKiDL is run in interactive mode.\n* Silenced errors/warnings when loading KiCad part description (.dcm) files.\n\n\n0.0.5 (2016-09-07)\n______________________\n\n* SKiDL now searches for parts with a user-configurable list of library search paths.\n* Part descriptions and keywords are now loaded from the .dcm file associated with a .lib file.\n\n\n0.0.4 (2016-08-27)\n______________________\n\n* SKiDL scripts can now output netlists in XML format.\n\n\n0.0.3 (2016-08-25)\n______________________\n\n* Added command-line utility to convert netlists into SKiDL programs.\n\n\n0.0.2 (2016-08-17)\n______________________\n\n* Changed the link to the documentation.\n\n\n0.0.1 (2016-08-16)\n______________________\n\n* First release on PyPI.", 
    "upload_time": "2017-02-17 01:15:12", 
    "lcname": "skidl", 
    "bugtrack_url": "", 
    "github": true, 
    "name": "skidl", 
    "license": "MIT", 
    "travis_ci": true, 
    "github_project": "skidl", 
    "summary": "A Python package for textually describing electronic circuit schematics.", 
    "split_keywords": [
        "skidl", 
        "electronic", 
        "circuit", 
        "schematics"
    ], 
    "author_email": "info@xess.com", 
    "urls": [
        {
            "has_sig": false, 
            "upload_time": "2017-02-17T01:15:12", 
            "comment_text": "", 
            "python_version": "source", 
            "url": "https://pypi.python.org/packages/77/32/344998a91166884448554521633a3ab373a01ae303c06d1c51c31defb0c6/skidl-0.0.9.zip", 
            "md5_digest": "e42e9e12d662d9e30208312ae5f92031", 
            "downloads": 0, 
            "filename": "skidl-0.0.9.zip", 
            "packagetype": "sdist", 
            "path": "77/32/344998a91166884448554521633a3ab373a01ae303c06d1c51c31defb0c6/skidl-0.0.9.zip", 
            "size": 431095
        }
    ], 
    "_id": null, 
    "cheesecake_installability_id": null
}