<div align="center">
<img src="https://devbisme.github.io/skidl/images/banner.png" alt="SKiDL Banner" width="100%">
</div>
**Never use a lousy schematic editor again!**
SKiDL is a Python package that lets you describe electronic circuits using code instead of schematic editors. Write your circuit as a Python program, and SKiDL outputs a netlist for PCB layout tools. It's "infrastructure as code" for electronics.
* Free software: MIT license
* Documentation: http://devbisme.github.io/skidl
* User Forum: https://github.com/devbisme/skidl/discussions
## Why SKiDL?
**Textual Circuit Design**: Use any text editor and enjoy version control with `git`, code reviews, and `diff` for circuit changes.
**Compact & Powerful**: Describe complex circuits in a fraction of the space. No more tracing signals across multi-page schematics.
**Reusable Design**: Share circuit modules on PyPI and GitHub. Create parametric "smart" circuits that adapt based on requirements.
**Design Automation**: Build circuits algorithmically. Generate repetitive structures, automatically size components, and create design variants programmatically.
**Electrical Rules Checking**: Catch common mistakes like unconnected pins, drive conflicts, and power connection errors.
**Hierarchical Design**: Mix linear, hierarchical, and modular design approaches as needed.
**Tool Independence**: Works with any PCB tool. Currently supports KiCad, but can be extended to other tools.
**Python Ecosystem**: Leverage Python's vast ecosystem for simulation, analysis, documentation, and automation.
## Quick Example
Here's a simple voltage divider that demonstrates SKiDL's syntax:
```python
from skidl import *
# Create input & output voltages and ground reference
vin, vout, gnd = Net('VI'), Net('VO'), Net('GND')
# Create two resistors with values and footprints
r1, r2 = 2 * Part("Device", 'R', dest=TEMPLATE, footprint='Resistor_SMD.pretty:R_0805_2012Metric')
r1.value, r2.value = '1K', '500'
# Connect the circuit elements.
vin & r1 & vout & r2 & gnd
# Or connect pin-by-pin if you prefer
# vin += r1[1]
# vout += r1[2], r2[1]
# gnd += r2[2]
# Check for errors and generate netlist
ERC()
generate_netlist(tool=KICAD9)
```
For a more complex example, here's a two-input AND gate built from discrete transistors:
```python
from skidl import *
# Create part templates
q = Part("Device", "Q_PNP_CBE", dest=TEMPLATE)
r = Part("Device", "R", dest=TEMPLATE)
# Create nets
gnd, vcc = Net("GND"), Net("VCC")
a, b, a_and_b = Net("A"), Net("B"), Net("A_AND_B")
# Instantiate parts
gndt = Part("power", "GND") # Ground terminal
vcct = Part("power", "VCC") # Power terminal
q1, q2 = q(2) # Two transistors
r1, r2, r3, r4, r5 = r(5, value="10K") # Five 10K resistors
# Make connections - notice the readable topology
a & r1 & q1["B C"] & r4 & q2["B C"] & a_and_b & r5 & gnd
b & r2 & q1["B"]
q1["C"] & r3 & gnd
vcc += q1["E"], q2["E"], vcct
gnd += gndt
generate_netlist(tool=KICAD9)
```
## Advanced Features
**Hierarchical Design**: Create reusable subcircuits and build complex systems from modular blocks.
**Part & Net Classes**: Apply design constraints, manufacturing requirements, and electrical specifications systematically.
**Smart Part Libraries**: Search parts by function, automatically assign footprints, and access any KiCad library.
**Multiple Output Formats**: Generate netlists for KiCad, XML for BOMs, or go directly to PCB layout.
**Visual Output**: Create SVG schematics, KiCad schematic files (currently V5 only), or DOT graphs for documentation.
**SPICE Integration**: Run simulations directly on your SKiDL circuits.
## Installation
```bash
pip install skidl
```
Set up KiCad library access (optional but recommended):
```bash
# Linux/Mac
export KICAD_SYMBOL_DIR="/usr/share/kicad/symbols"
# Windows
set KICAD_SYMBOL_DIR=C:\Program Files\KiCad\share\kicad\symbols
```
## Getting Started
1. **Learn the basics**: Check out the [documentation](http://devbisme.github.io/skidl) for comprehensive tutorials
2. **Try examples**: Explore the `tests/examples/` directory in the repository
3. **Get help**: Join discussions in our [user forum](https://github.com/devbisme/skidl/discussions)
4. **Convert existing designs**: Use the `netlist_to_skidl` tool to convert KiCad designs to SKiDL
# History
## 2.1.1 (2025-08-31)
- Added a cheatsheet for SKiDL 2.1.0.
- Fixed error in PyPi installation.
## 2.1.0 (2025-08-30)
- Fixed #238: tstamps were incorrectly generated for netlist files.
- [netlist_to_skidl]{.title-ref} now generates hierarchical SKiDL code
that mirrors the hierarchy found in the netlist.
- Parts can be assigned a part class that stores attributes for a set of
parts.
- Nets can be assigned a net class that stores attributes for a set of
nets.
- [SubCircuits]{.title-ref} have taken over the [Group]{.title-ref}
functionality. ([Group]{.title-ref} has been maintained for backwards
compatibility.)
- [Circuits]{.title-ref} now include a tree of [Node]{.title-ref}
objects that stores the hierarchical structure.
- Improved tracking of netlist objects back to the source line where
they were instantiated.
- InSpice has replaced PySpice to allow the use of newer versions of the
ngspice simulator.
- [KICAD9]{.title-ref} tool identifier added to support KiCad 9.
## 2.0.1 (2024-12-11)
- Fixed #233: Imported [active_logger]{.title-ref} into
generate_schematic.py of KiCad 6, 7, 8.
- Fixed #235: Removed merging of multi-segment nets when generating
netlists, XML, SVG, DOT because it removes pins from existing net
references. Only merge for schematic generation or SPICE simulation.
## 2.0.0 (2024-11-27)
- No longer compatible with Python 2.
- [\@package]{.title-ref} decorator removed.
- Additional [Part]{.title-ref} attributes can be specified when
exporting libraries.
- Added [unexpio]{.title-ref} dict to [Interface]{.title-ref} objects
for accessing I/O without buses expanded into individual nets.
- Added connect() and \_\_iadd\_\_() methods to interconnect
[Interface]{.title-ref} objects.
- Part libraries are pickled when first loaded for faster access on
subsequent accesses. The directory for storing the pickled library
files is specified in the SKiDL configuration file.
- The [KICAD]{.title-ref} tool identifier now points to
[KICAD8]{.title-ref}.
## 1.2.2 (2024-07-13)
- Added SVG schematic generation feature for KiCad 6, 7, and 8.
- Added backend tool identifiers of [KICAD5]{.title-ref},
[KICAD6]{.title-ref}, [KICAD7]{.title-ref}, and [KICAD8]{.title-ref}.
- For compatibility, [KICAD]{.title-ref} tool identifier points to
[KICAD5]{.title-ref}.
## 1.2.1 (2023-07-26)
- [is_url]{.title-ref} function fixed to solve problems with
[search]{.title-ref} and loading libraries.
## 1.2.0 (2023-07-14)
- Added ability to generate an editable schematic from a Circuit object.
(Currently only works for KiCad V5.)
- Added Group object for creating hierarchy without using function
calls.
- [generate_pcb]{.title-ref} now takes an optional list of footprint
library directories.
- If not explicitly declared, [Part]{.title-ref} objects will load the
default footprint from their symbol definition.
- Added [empty_footprint_handler()]{.title-ref} for parts without
footprints that logs errors by default but can be overriden by the
user.
- Symbol libraries can now be searched on remote repositories by placing
the URL in the [lib_search_paths]{.title-ref} dictionary. KiCad V6
symbols are found at
[https://gitlab.com/kicad/libraries/kicad-symbols/-/raw/master]{.title-ref}
and V5 symbols are at
[https://raw.githubusercontent.com/KiCad/kicad-symbols/master/]{.title-ref}.
- [Part]{.title-ref} pins can now be sorted and retrieved in order using
the [ordered_pins]{.title-ref} property.
## 1.1.0 (2021-10-22)
- Added [generate_pcb()]{.title-ref} function to create a PCB file
directly from a [Circuit]{.title-ref} object. (Currently only works
for KiCad.)
- Added [PartTmplt]{.title-ref} shortcut which creates a Part template
using [dest=TEMPLATE]{.title-ref} implicitly.
## 1.0.0 (2021-05-09)
- Buses can now be created without names and a name will be
automatically assigned. Or use \"name=\...\" to manually assign a
name. Or just place a string in the list of arguments and that will be
used.
- Footprint search can now process directories of footprints without the
need for an [fp-lib-table]{.title-ref} file.
- [Part]{.title-ref} fields can now be accessed using attributes.
- Creating fields requires use of [Part.fields\[key\]]{.title-ref}
instead of Part.key.
- Added context manager for [Circuit]{.title-ref} object so Parts/Nets
can be joined using a [with\...]{.title-ref} statement.
- Adding/removing [Parts]{.title-ref} to/from a [Circuit]{.title-ref}
can now be done using [+=]{.title-ref} and [-=]{.title-ref}.
- Tags can be added to [Parts]{.title-ref} and [Circuits]{.title-ref}
for hierarchical naming.
- [Part]{.title-ref} values can now be assigned arbitrary objects
including units from either PySpice or Pint.
- Multi-function pin names can now be split into a collection of shorter
aliases, thus reducing the need to access pins using regexes.
- Schematics can now be automatically using the KiCad symbol graphics
for the parts.
- The library interface now handles the Skywater 130 SPICE libraries.
## 0.0.30 (2020-05-16)
- Added \@package decorator to make subcircuits act like Parts.
- Interfaces now act like dictionaries so the \*\* operator works as
expected.
- Interface I/O can now be accessed using brackets (\[\]) and via
attributes (e.g., intfc.a).
- Interface I/O can now be assigned aliases.
- Added tee() function for creating T-junctions in networks.
- Custom ERCs can now be added using the [erc_assert]{.title-ref}
function.
- Aliases take precedence over default pin names.
- Substring matching in pin names can be enabled/disabled (off by
default).
## 0.0.29 (2020-01-30)
- Added XSPICE parts capability to SPICE simulations.
- Unconnected XSPICE ports now are set to NULL in SPICE node lists.
- Added no_files() function to disable output to files of netlists,
ERCs, logs, backup libs.
## 0.0.28 (2019-12-17)
- The `zyc` utility was split into a separate repository and placed on
PyPi.
- Fixed slicing of grouped part pins so things like `ram['A[1]']` won\'t
grab `A1`, `A10`, `A11`, etc.
## 0.0.27 (2019-12-16)
- Prevent changing the name of net 0 when generating a SPICE netlist.
- Fixed Pin, Net, Bus and Part iterators so they\'ll work in nested
loops.
- Part units are automatically added when a part is parsed.
- Files are now opened for reading using latin_1 encoding to allow
special symbols used by KiCad.
- Part pins can now be aliased directly, e.g. [uc\[5\].aliases +=
\'gp0\']{.title-ref}.
- Added class method get() to Part to allow finding a part based on
name, reference, description.
- Refactored ERC functions to allow user-extensibility.
- Created a base object for Circuit, Part, Pin, Net, and Bus objects.
- Added an aliases property to the SKiDL base object so all its children
could be aliased.
- Updated to perform simulations with ngspice version 30.
- Added a notes property to allow attachment of user notes to Parts,
Pins, Nets, etc.
- Added net class to net objects for specifying net-specific design
rules in PCBNEW.
- Ignore multiple pins with the same number in symbols with DeMorgan
equivalents.
- Fixed problem with non-ASCII chars (e.g. Ohms) in strings.
- Sped-up part/net naming using heap/cache, binary search, sets.
- Sped-up by storing net traversals to avoid recomputation.
- Fixed processing of slices in things like sdram\[\'A\[0:15\]\'\].
- Sped-up part_search() by eliminating unnecessary part parsing.
- Improved schematic generation with graphviz.
- Search now allows AND/OR of parenthesized terms.
- New GUI for searching for parts and footprints.
- Footprint libraries to search are now selected from the global
fp-lib-table file.
- KiCad library component field values are now stored in a dict in Part
indexed by the field name or F0, F1, F2\...
- KiCad library component field values are also stored as Part
attributes using the field name or F0, F1, F2\...
- Added [p]{.title-ref} and [n]{.title-ref} attributes to
[Part]{.title-ref} object to permit explicit reference to pin numbers
or names.
## 0.0.26 (2019-01-25)
- `search` command no longer looks in backup library because that leads
to erroneous hits in all libraries.
- Part objects will now iterate through their pins and len() will return
the number of pins.
- Updated netlist_to_skidl utility to account for new version of
kinparse.
## 0.0.25 (2018-12-30)
- Updated website.
- KISYSMOD is no longer used to find part libraries, only
KICAD_SYMBOL_DIR is used now.
## 0.0.24 (2018-09-15)
- Fixed an error where creating a backup part library for a design would
create extra pins attached to the nets.
## 0.0.23 (2018-08-25)
- Added Network objects to make it easy to create serial & parallel
combinations of two-pin parts.
- SKiDL design hierarchy is now embedded in the KiCad netlist that\'s
generated.
## 0.0.22 (2018-05-XX)
- Added Interface objects for storing complicated sets of I/O signals
for subsystems.
- ERC no longer redundantly checks every segment of a multi-segment net
and reports multiple errors.
- copy() function of Part, Bus, Pin, Net objects now returns a scalar
object while copy(1) returns a list with one object.
- Bus, Pin, and Net objects now have iterators.
- Corrected initialization of KiCad library search paths.
------------------------------------------------------------------------
## 0.0.21 (2018-04-30)
- Added pull() and fetch() methods for getting/creating existing/new Net
and Bus objects.
- Added drive property to pins to override their default pin function
attribute.
- Part pins and units can now be accessed as attributes.
- Nets, pins, and buses now support the width property.
- Indexing with brackets now works equivalently for pins, nets, and
buses.
- Grouped part pins (such as address and data buses) can now be accessed
using a slice-like notation, e.g. memory\[\'ADDR\[0:7\]\'\].
## 0.0.20 (2018-03-08)
- Matching of pin lists now begins with normal string matching before
using regexes.
- Added more tests and fixed existing tests.
## 0.0.19 (2018-02-20)
- Selecting part pins now looks for exact match before falling back to
regex matching.
- PySpice now needs to be manually installed to perform SPICE
simulations.
- SPICE simulations of subcircuits (.SUBCKT) now supported.
- Improvements/additions to the library of supported SPICE parts.
## 0.0.18 (2018-02-07)
- SPICE simulations of circuits now supported (Python 3 only).
## 0.0.17 (2018-01-23)
- Modularized code into separate files.
## 0.0.16 (2018-01-16)
- Parsing of KiCad EESchema libraries made more robust.
- DEFAULT_TOOL replaced with set_default_tool() function.
- Some code simplification by using a context manager for opening files.
## 0.0.15 (2018-01-09)
- Testing made more robust.
## 0.0.14 (2018-01-05)
- KiCad netlists are now parsed using the external package kinparse.
- Cleaned-up pylint-identified issues.
- Removed absolute file paths to libraries from tests.
## 0.0.13 (2017-08-20)
- Fixed problem where the search function was only returning parts found
in the last library searched.
## 0.0.12 (2017-04-20)
- Use of builtin now works with Python 2 & 3.
- Started using namedtuple in some places (like net traversal) for
clarity.
- Corrected pin-to-pin connections so if a net is created, it goes into
the same Circuit the pins are members of.
- Part templates can now contain a reference to a Circuit object that
will be applied when the template is instantiated.
- When pins are connected to nets, or nets to nets, the resulting set of
connected nets are all given the same name.
- Buses are not added to a Circuit object if they are already members of
it. This fix caused the next problem.
- Buses weren\'t getting added to the Circuit object because they
already contained a reference to the Circuit. Fixed by clearing ref
before adding to Circuit.
- Created mini_reset() method to clear circuitry without clearing
library cache so the libraries don\'t have to be loaded again (slow).
- search() utility now prints the names of libraries as they are
searched so user sees progress.
- Fixed exceptions if part definition contained non-unicode stuff.
- Hide exceptions that occur when using the show() utility.
- More tests added for NC nets and hand-crafted parts.
- default_circuit and the NC net for the active circuit are now made
accessible in all modules using \_\_builtin\_\_.
- Corrected error messages that referenced wrong/non-existing variable.
- Inserted NO_LIB for the library if it doesn\'t exist when generating
KiCad netlists or XML.
- Attributes can now be passed when creating a Circuit object.
- Pins are now associated with part when added to the part.
- Minimum and maximum pins for a part are now computed as needed.
- Each Circuit object now has its own NC net.
- Added tests for bus movement and copying.
- Implemented bus movement between Circuit objects.
- Additional test cases were created.
- Nets and Parts can now be removed from Circuits.
- The circuit that pins and nets are in is now checked before
connections are made so cross-circuit connections are not created.
- Default members were added to Pin and Part objects so they would
always exist and not cause errors when missing.
- Implemented moving Parts and Nets from one circuit to another
(almost).
- Nets with no attached pins are now added to a circuit.
- Re-wrote some tests to account for the presence of no-pin nets in a
circuit.
- A class method was missing its \'self\' argument.
- Fixed \@subcircuit decorator so it won\'t cause an error if the
function it decorates doesn\'t have a \'circuit\' keyword argument.
- Split the unit tests across multiple files. Added setup/teardown code.
- Added capability to create multiple, independent Circuit objects to
which Parts and Nets can be assigned. The default circuit is still the
target if not Circuit is explicitly referenced.
- Added IOError to exception list for opening a SKiDL part library.
## 0.0.11 (2017-04-04)
- Part libraries in SKiDL format are now supported.
- Parts can now be created on-the-fly and instantiated or added to
libraries.
- The parts used in a circuit can be stored in a backup SKiDL library
and used if the original libraries are missing.
- The KiCad standard part libraries were converted to SKiDL libraries
and placed in skidl.libs.
## 0.0.10 (2017-03-13)
- Nets without pins can now be merged.
- Parts and Pins are now sorted when netlists are generated.
- For an existing Bus, new bus lines can be inserted at any position or
the bus can be extended.
## 0.0.9 (2017-02-16)
- Use getattr() instead of \_\_class\_\_.\_\_dict\_\_ so that subclasses
of SKiDL objects can find attributes named within strings without
searching the \_\_mor\_\_.
## 0.0.8 (2017-01-11)
- skidl_to_netlist now uses templates.
- Default operation of search() is now less exacting.
- Traceback is now suppressed if show() is passed a part name not in a
library.
## 0.0.7 (2016-09-11)
- Lack of KISYSMOD environment variable no longer causes an exception.
- requirements.txt file now references the requirements from setup.py.
- Changed setup so it generates a pckg_info file with version, author,
email.
## 0.0.6 (2016-09-10)
- Fixed error caused when trying to find script name when SKiDL is run
in interactive mode.
- Silenced errors/warnings when loading KiCad part description (.dcm)
files.
## 0.0.5 (2016-09-07)
- SKiDL now searches for parts with a user-configurable list of library
search paths.
- Part descriptions and keywords are now loaded from the .dcm file
associated with a .lib file.
## 0.0.4 (2016-08-27)
- SKiDL scripts can now output netlists in XML format.
## 0.0.3 (2016-08-25)
- Added command-line utility to convert netlists into SKiDL programs.
## 0.0.2 (2016-08-17)
- Changed the link to the documentation.
## 0.0.1 (2016-08-16)
- First release on PyPI.
Raw data
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"description": "<div align=\"center\">\n <img src=\"https://devbisme.github.io/skidl/images/banner.png\" alt=\"SKiDL Banner\" width=\"100%\">\n</div>\n\n\n\n\n\n\n\n\n\n\n**Never use a lousy schematic editor again!**\n\nSKiDL is a Python package that lets you describe electronic circuits using code instead of schematic editors. Write your circuit as a Python program, and SKiDL outputs a netlist for PCB layout tools. It's \"infrastructure as code\" for electronics.\n\n* Free software: MIT license\n* Documentation: http://devbisme.github.io/skidl\n* User Forum: https://github.com/devbisme/skidl/discussions\n\n## Why SKiDL?\n\n**Textual Circuit Design**: Use any text editor and enjoy version control with `git`, code reviews, and `diff` for circuit changes.\n\n**Compact & Powerful**: Describe complex circuits in a fraction of the space. No more tracing signals across multi-page schematics.\n\n**Reusable Design**: Share circuit modules on PyPI and GitHub. Create parametric \"smart\" circuits that adapt based on requirements.\n\n**Design Automation**: Build circuits algorithmically. Generate repetitive structures, automatically size components, and create design variants programmatically.\n\n**Electrical Rules Checking**: Catch common mistakes like unconnected pins, drive conflicts, and power connection errors.\n\n**Hierarchical Design**: Mix linear, hierarchical, and modular design approaches as needed.\n\n**Tool Independence**: Works with any PCB tool. Currently supports KiCad, but can be extended to other tools.\n\n**Python Ecosystem**: Leverage Python's vast ecosystem for simulation, analysis, documentation, and automation.\n\n## Quick Example\n\nHere's a simple voltage divider that demonstrates SKiDL's syntax:\n\n```python\nfrom skidl import *\n\n# Create input & output voltages and ground reference\nvin, vout, gnd = Net('VI'), Net('VO'), Net('GND')\n\n# Create two resistors with values and footprints\nr1, r2 = 2 * Part(\"Device\", 'R', dest=TEMPLATE, footprint='Resistor_SMD.pretty:R_0805_2012Metric')\nr1.value, r2.value = '1K', '500'\n\n# Connect the circuit elements.\nvin & r1 & vout & r2 & gnd\n\n# Or connect pin-by-pin if you prefer\n# vin += r1[1]\n# vout += r1[2], r2[1] \n# gnd += r2[2]\n\n# Check for errors and generate netlist\nERC()\ngenerate_netlist(tool=KICAD9)\n```\n\nFor a more complex example, here's a two-input AND gate built from discrete transistors:\n\n\n\n```python\nfrom skidl import *\n\n# Create part templates\nq = Part(\"Device\", \"Q_PNP_CBE\", dest=TEMPLATE)\nr = Part(\"Device\", \"R\", dest=TEMPLATE)\n\n# Create nets\ngnd, vcc = Net(\"GND\"), Net(\"VCC\")\na, b, a_and_b = Net(\"A\"), Net(\"B\"), Net(\"A_AND_B\")\n\n# Instantiate parts\ngndt = Part(\"power\", \"GND\") # Ground terminal\nvcct = Part(\"power\", \"VCC\") # Power terminal\nq1, q2 = q(2) # Two transistors\nr1, r2, r3, r4, r5 = r(5, value=\"10K\") # Five 10K resistors\n\n# Make connections - notice the readable topology\na & r1 & q1[\"B C\"] & r4 & q2[\"B C\"] & a_and_b & r5 & gnd\nb & r2 & q1[\"B\"]\nq1[\"C\"] & r3 & gnd\nvcc += q1[\"E\"], q2[\"E\"], vcct\ngnd += gndt\n\ngenerate_netlist(tool=KICAD9)\n```\n\n## Advanced Features\n\n**Hierarchical Design**: Create reusable subcircuits and build complex systems from modular blocks.\n\n**Part & Net Classes**: Apply design constraints, manufacturing requirements, and electrical specifications systematically.\n\n**Smart Part Libraries**: Search parts by function, automatically assign footprints, and access any KiCad library.\n\n**Multiple Output Formats**: Generate netlists for KiCad, XML for BOMs, or go directly to PCB layout.\n\n**Visual Output**: Create SVG schematics, KiCad schematic files (currently V5 only), or DOT graphs for documentation.\n\n**SPICE Integration**: Run simulations directly on your SKiDL circuits.\n\n## Installation\n\n```bash\npip install skidl\n```\n\nSet up KiCad library access (optional but recommended):\n\n```bash\n# Linux/Mac\nexport KICAD_SYMBOL_DIR=\"/usr/share/kicad/symbols\"\n\n# Windows \nset KICAD_SYMBOL_DIR=C:\\Program Files\\KiCad\\share\\kicad\\symbols\n```\n\n## Getting Started\n\n1. **Learn the basics**: Check out the [documentation](http://devbisme.github.io/skidl) for comprehensive tutorials\n2. **Try examples**: Explore the `tests/examples/` directory in the repository\n3. **Get help**: Join discussions in our [user forum](https://github.com/devbisme/skidl/discussions)\n4. **Convert existing designs**: Use the `netlist_to_skidl` tool to convert KiCad designs to SKiDL\n\n\n\n# History\n\n## 2.1.1 (2025-08-31)\n\n- Added a cheatsheet for SKiDL 2.1.0.\n- Fixed error in PyPi installation.\n\n## 2.1.0 (2025-08-30)\n\n- Fixed #238: tstamps were incorrectly generated for netlist files.\n- [netlist_to_skidl]{.title-ref} now generates hierarchical SKiDL code\n that mirrors the hierarchy found in the netlist.\n- Parts can be assigned a part class that stores attributes for a set of\n parts.\n- Nets can be assigned a net class that stores attributes for a set of\n nets.\n- [SubCircuits]{.title-ref} have taken over the [Group]{.title-ref}\n functionality. ([Group]{.title-ref} has been maintained for backwards\n compatibility.)\n- [Circuits]{.title-ref} now include a tree of [Node]{.title-ref}\n objects that stores the hierarchical structure.\n- Improved tracking of netlist objects back to the source line where\n they were instantiated.\n- InSpice has replaced PySpice to allow the use of newer versions of the\n ngspice simulator.\n- [KICAD9]{.title-ref} tool identifier added to support KiCad 9.\n\n## 2.0.1 (2024-12-11)\n\n- Fixed #233: Imported [active_logger]{.title-ref} into\n generate_schematic.py of KiCad 6, 7, 8.\n- Fixed #235: Removed merging of multi-segment nets when generating\n netlists, XML, SVG, DOT because it removes pins from existing net\n references. Only merge for schematic generation or SPICE simulation.\n\n## 2.0.0 (2024-11-27)\n\n- No longer compatible with Python 2.\n- [\\@package]{.title-ref} decorator removed.\n- Additional [Part]{.title-ref} attributes can be specified when\n exporting libraries.\n- Added [unexpio]{.title-ref} dict to [Interface]{.title-ref} objects\n for accessing I/O without buses expanded into individual nets.\n- Added connect() and \\_\\_iadd\\_\\_() methods to interconnect\n [Interface]{.title-ref} objects.\n- Part libraries are pickled when first loaded for faster access on\n subsequent accesses. The directory for storing the pickled library\n files is specified in the SKiDL configuration file.\n- The [KICAD]{.title-ref} tool identifier now points to\n [KICAD8]{.title-ref}.\n\n## 1.2.2 (2024-07-13)\n\n- Added SVG schematic generation feature for KiCad 6, 7, and 8.\n- Added backend tool identifiers of [KICAD5]{.title-ref},\n [KICAD6]{.title-ref}, [KICAD7]{.title-ref}, and [KICAD8]{.title-ref}.\n- For compatibility, [KICAD]{.title-ref} tool identifier points to\n [KICAD5]{.title-ref}.\n\n## 1.2.1 (2023-07-26)\n\n- [is_url]{.title-ref} function fixed to solve problems with\n [search]{.title-ref} and loading libraries.\n\n## 1.2.0 (2023-07-14)\n\n- Added ability to generate an editable schematic from a Circuit object.\n (Currently only works for KiCad V5.)\n- Added Group object for creating hierarchy without using function\n calls.\n- [generate_pcb]{.title-ref} now takes an optional list of footprint\n library directories.\n- If not explicitly declared, [Part]{.title-ref} objects will load the\n default footprint from their symbol definition.\n- Added [empty_footprint_handler()]{.title-ref} for parts without\n footprints that logs errors by default but can be overriden by the\n user.\n- Symbol libraries can now be searched on remote repositories by placing\n the URL in the [lib_search_paths]{.title-ref} dictionary. KiCad V6\n symbols are found at\n [https://gitlab.com/kicad/libraries/kicad-symbols/-/raw/master]{.title-ref}\n and V5 symbols are at\n [https://raw.githubusercontent.com/KiCad/kicad-symbols/master/]{.title-ref}.\n- [Part]{.title-ref} pins can now be sorted and retrieved in order using\n the [ordered_pins]{.title-ref} property.\n\n## 1.1.0 (2021-10-22)\n\n- Added [generate_pcb()]{.title-ref} function to create a PCB file\n directly from a [Circuit]{.title-ref} object. (Currently only works\n for KiCad.)\n- Added [PartTmplt]{.title-ref} shortcut which creates a Part template\n using [dest=TEMPLATE]{.title-ref} implicitly.\n\n## 1.0.0 (2021-05-09)\n\n- Buses can now be created without names and a name will be\n automatically assigned. Or use \\\"name=\\...\\\" to manually assign a\n name. Or just place a string in the list of arguments and that will be\n used.\n- Footprint search can now process directories of footprints without the\n need for an [fp-lib-table]{.title-ref} file.\n- [Part]{.title-ref} fields can now be accessed using attributes.\n- Creating fields requires use of [Part.fields\\[key\\]]{.title-ref}\n instead of Part.key.\n- Added context manager for [Circuit]{.title-ref} object so Parts/Nets\n can be joined using a [with\\...]{.title-ref} statement.\n- Adding/removing [Parts]{.title-ref} to/from a [Circuit]{.title-ref}\n can now be done using [+=]{.title-ref} and [-=]{.title-ref}.\n- Tags can be added to [Parts]{.title-ref} and [Circuits]{.title-ref}\n for hierarchical naming.\n- [Part]{.title-ref} values can now be assigned arbitrary objects\n including units from either PySpice or Pint.\n- Multi-function pin names can now be split into a collection of shorter\n aliases, thus reducing the need to access pins using regexes.\n- Schematics can now be automatically using the KiCad symbol graphics\n for the parts.\n- The library interface now handles the Skywater 130 SPICE libraries.\n\n## 0.0.30 (2020-05-16)\n\n- Added \\@package decorator to make subcircuits act like Parts.\n- Interfaces now act like dictionaries so the \\*\\* operator works as\n expected.\n- Interface I/O can now be accessed using brackets (\\[\\]) and via\n attributes (e.g., intfc.a).\n- Interface I/O can now be assigned aliases.\n- Added tee() function for creating T-junctions in networks.\n- Custom ERCs can now be added using the [erc_assert]{.title-ref}\n function.\n- Aliases take precedence over default pin names.\n- Substring matching in pin names can be enabled/disabled (off by\n default).\n\n## 0.0.29 (2020-01-30)\n\n- Added XSPICE parts capability to SPICE simulations.\n- Unconnected XSPICE ports now are set to NULL in SPICE node lists.\n- Added no_files() function to disable output to files of netlists,\n ERCs, logs, backup libs.\n\n## 0.0.28 (2019-12-17)\n\n- The `zyc` utility was split into a separate repository and placed on\n PyPi.\n- Fixed slicing of grouped part pins so things like `ram['A[1]']` won\\'t\n grab `A1`, `A10`, `A11`, etc.\n\n## 0.0.27 (2019-12-16)\n\n- Prevent changing the name of net 0 when generating a SPICE netlist.\n- Fixed Pin, Net, Bus and Part iterators so they\\'ll work in nested\n loops.\n- Part units are automatically added when a part is parsed.\n- Files are now opened for reading using latin_1 encoding to allow\n special symbols used by KiCad.\n- Part pins can now be aliased directly, e.g. [uc\\[5\\].aliases +=\n \\'gp0\\']{.title-ref}.\n- Added class method get() to Part to allow finding a part based on\n name, reference, description.\n- Refactored ERC functions to allow user-extensibility.\n- Created a base object for Circuit, Part, Pin, Net, and Bus objects.\n- Added an aliases property to the SKiDL base object so all its children\n could be aliased.\n- Updated to perform simulations with ngspice version 30.\n- Added a notes property to allow attachment of user notes to Parts,\n Pins, Nets, etc.\n- Added net class to net objects for specifying net-specific design\n rules in PCBNEW.\n- Ignore multiple pins with the same number in symbols with DeMorgan\n equivalents.\n- Fixed problem with non-ASCII chars (e.g. Ohms) in strings.\n- Sped-up part/net naming using heap/cache, binary search, sets.\n- Sped-up by storing net traversals to avoid recomputation.\n- Fixed processing of slices in things like sdram\\[\\'A\\[0:15\\]\\'\\].\n- Sped-up part_search() by eliminating unnecessary part parsing.\n- Improved schematic generation with graphviz.\n- Search now allows AND/OR of parenthesized terms.\n- New GUI for searching for parts and footprints.\n- Footprint libraries to search are now selected from the global\n fp-lib-table file.\n- KiCad library component field values are now stored in a dict in Part\n indexed by the field name or F0, F1, F2\\...\n- KiCad library component field values are also stored as Part\n attributes using the field name or F0, F1, F2\\...\n- Added [p]{.title-ref} and [n]{.title-ref} attributes to\n [Part]{.title-ref} object to permit explicit reference to pin numbers\n or names.\n\n## 0.0.26 (2019-01-25)\n\n- `search` command no longer looks in backup library because that leads\n to erroneous hits in all libraries.\n- Part objects will now iterate through their pins and len() will return\n the number of pins.\n- Updated netlist_to_skidl utility to account for new version of\n kinparse.\n\n## 0.0.25 (2018-12-30)\n\n- Updated website.\n- KISYSMOD is no longer used to find part libraries, only\n KICAD_SYMBOL_DIR is used now.\n\n## 0.0.24 (2018-09-15)\n\n- Fixed an error where creating a backup part library for a design would\n create extra pins attached to the nets.\n\n## 0.0.23 (2018-08-25)\n\n- Added Network objects to make it easy to create serial & parallel\n combinations of two-pin parts.\n- SKiDL design hierarchy is now embedded in the KiCad netlist that\\'s\n generated.\n\n## 0.0.22 (2018-05-XX)\n\n- Added Interface objects for storing complicated sets of I/O signals\n for subsystems.\n- ERC no longer redundantly checks every segment of a multi-segment net\n and reports multiple errors.\n- copy() function of Part, Bus, Pin, Net objects now returns a scalar\n object while copy(1) returns a list with one object.\n- Bus, Pin, and Net objects now have iterators.\n- Corrected initialization of KiCad library search paths.\n\n------------------------------------------------------------------------\n\n## 0.0.21 (2018-04-30)\n\n- Added pull() and fetch() methods for getting/creating existing/new Net\n and Bus objects.\n- Added drive property to pins to override their default pin function\n attribute.\n- Part pins and units can now be accessed as attributes.\n- Nets, pins, and buses now support the width property.\n- Indexing with brackets now works equivalently for pins, nets, and\n buses.\n- Grouped part pins (such as address and data buses) can now be accessed\n using a slice-like notation, e.g. memory\\[\\'ADDR\\[0:7\\]\\'\\].\n\n## 0.0.20 (2018-03-08)\n\n- Matching of pin lists now begins with normal string matching before\n using regexes.\n- Added more tests and fixed existing tests.\n\n## 0.0.19 (2018-02-20)\n\n- Selecting part pins now looks for exact match before falling back to\n regex matching.\n- PySpice now needs to be manually installed to perform SPICE\n simulations.\n- SPICE simulations of subcircuits (.SUBCKT) now supported.\n- Improvements/additions to the library of supported SPICE parts.\n\n## 0.0.18 (2018-02-07)\n\n- SPICE simulations of circuits now supported (Python 3 only).\n\n## 0.0.17 (2018-01-23)\n\n- Modularized code into separate files.\n\n## 0.0.16 (2018-01-16)\n\n- Parsing of KiCad EESchema libraries made more robust.\n- DEFAULT_TOOL replaced with set_default_tool() function.\n- Some code simplification by using a context manager for opening files.\n\n## 0.0.15 (2018-01-09)\n\n- Testing made more robust.\n\n## 0.0.14 (2018-01-05)\n\n- KiCad netlists are now parsed using the external package kinparse.\n- Cleaned-up pylint-identified issues.\n- Removed absolute file paths to libraries from tests.\n\n## 0.0.13 (2017-08-20)\n\n- Fixed problem where the search function was only returning parts found\n in the last library searched.\n\n## 0.0.12 (2017-04-20)\n\n- Use of builtin now works with Python 2 & 3.\n- Started using namedtuple in some places (like net traversal) for\n clarity.\n- Corrected pin-to-pin connections so if a net is created, it goes into\n the same Circuit the pins are members of.\n- Part templates can now contain a reference to a Circuit object that\n will be applied when the template is instantiated.\n- When pins are connected to nets, or nets to nets, the resulting set of\n connected nets are all given the same name.\n- Buses are not added to a Circuit object if they are already members of\n it. This fix caused the next problem.\n- Buses weren\\'t getting added to the Circuit object because they\n already contained a reference to the Circuit. Fixed by clearing ref\n before adding to Circuit.\n- Created mini_reset() method to clear circuitry without clearing\n library cache so the libraries don\\'t have to be loaded again (slow).\n- search() utility now prints the names of libraries as they are\n searched so user sees progress.\n- Fixed exceptions if part definition contained non-unicode stuff.\n- Hide exceptions that occur when using the show() utility.\n- More tests added for NC nets and hand-crafted parts.\n- default_circuit and the NC net for the active circuit are now made\n accessible in all modules using \\_\\_builtin\\_\\_.\n- Corrected error messages that referenced wrong/non-existing variable.\n- Inserted NO_LIB for the library if it doesn\\'t exist when generating\n KiCad netlists or XML.\n- Attributes can now be passed when creating a Circuit object.\n- Pins are now associated with part when added to the part.\n- Minimum and maximum pins for a part are now computed as needed.\n- Each Circuit object now has its own NC net.\n- Added tests for bus movement and copying.\n- Implemented bus movement between Circuit objects.\n- Additional test cases were created.\n- Nets and Parts can now be removed from Circuits.\n- The circuit that pins and nets are in is now checked before\n connections are made so cross-circuit connections are not created.\n- Default members were added to Pin and Part objects so they would\n always exist and not cause errors when missing.\n- Implemented moving Parts and Nets from one circuit to another\n (almost).\n- Nets with no attached pins are now added to a circuit.\n- Re-wrote some tests to account for the presence of no-pin nets in a\n circuit.\n- A class method was missing its \\'self\\' argument.\n- Fixed \\@subcircuit decorator so it won\\'t cause an error if the\n function it decorates doesn\\'t have a \\'circuit\\' keyword argument.\n- Split the unit tests across multiple files. Added setup/teardown code.\n- Added capability to create multiple, independent Circuit objects to\n which Parts and Nets can be assigned. The default circuit is still the\n target if not Circuit is explicitly referenced.\n- Added IOError to exception list for opening a SKiDL part library.\n\n## 0.0.11 (2017-04-04)\n\n- Part libraries in SKiDL format are now supported.\n- Parts can now be created on-the-fly and instantiated or added to\n libraries.\n- The parts used in a circuit can be stored in a backup SKiDL library\n and used if the original libraries are missing.\n- The KiCad standard part libraries were converted to SKiDL libraries\n and placed in skidl.libs.\n\n## 0.0.10 (2017-03-13)\n\n- Nets without pins can now be merged.\n- Parts and Pins are now sorted when netlists are generated.\n- For an existing Bus, new bus lines can be inserted at any position or\n the bus can be extended.\n\n## 0.0.9 (2017-02-16)\n\n- Use getattr() instead of \\_\\_class\\_\\_.\\_\\_dict\\_\\_ so that subclasses\n of SKiDL objects can find attributes named within strings without\n searching the \\_\\_mor\\_\\_.\n\n## 0.0.8 (2017-01-11)\n\n- skidl_to_netlist now uses templates.\n- Default operation of search() is now less exacting.\n- Traceback is now suppressed if show() is passed a part name not in a\n library.\n\n## 0.0.7 (2016-09-11)\n\n- Lack of KISYSMOD environment variable no longer causes an exception.\n- requirements.txt file now references the requirements from setup.py.\n- Changed setup so it generates a pckg_info file with version, author,\n email.\n\n## 0.0.6 (2016-09-10)\n\n- Fixed error caused when trying to find script name when SKiDL is run\n in interactive mode.\n- Silenced errors/warnings when loading KiCad part description (.dcm)\n files.\n\n## 0.0.5 (2016-09-07)\n\n- SKiDL now searches for parts with a user-configurable list of library\n search paths.\n- Part descriptions and keywords are now loaded from the .dcm file\n associated with a .lib file.\n\n## 0.0.4 (2016-08-27)\n\n- SKiDL scripts can now output netlists in XML format.\n\n## 0.0.3 (2016-08-25)\n\n- Added command-line utility to convert netlists into SKiDL programs.\n\n## 0.0.2 (2016-08-17)\n\n- Changed the link to the documentation.\n\n## 0.0.1 (2016-08-16)\n\n- First release on PyPI.\n",
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