tsfpga


Nametsfpga JSON
Version 12.3.1 PyPI version JSON
download
home_page
SummaryA flexible and scalable development platform for modern FPGA projects
upload_time2024-03-08 09:33:37
maintainer
docs_urlNone
authorLukas Vik
requires_python>=3.9
licenseBSD 3-Clause License
keywords asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit
VCS
bugtrack_url
requirements No requirements were recorded.
Travis-CI No Travis.
coveralls test coverage No coveralls.
            .. image:: https://tsfpga.com/logos/banner.png
  :alt: Project banner
  :align: center

|

.. |pic_website| image:: https://tsfpga.com/badges/website.svg
  :alt: Website
  :target: https://tsfpga.com

.. |pic_repository| image:: https://tsfpga.com/badges/repository.svg
  :alt: Repository
  :target: https://github.com/tsfpga/tsfpga

.. |pic_chat| image:: https://tsfpga.com/badges/chat.svg
  :alt: Chat
  :target: https://github.com/tsfpga/tsfpga/discussions

.. |pic_pip_install| image:: https://tsfpga.com/badges/pip_install.svg
  :alt: pypi
  :target: https://pypi.org/project/tsfpga/

.. |pic_license| image:: https://tsfpga.com/badges/license.svg
  :alt: License
  :target: https://tsfpga.com/license_information.html

.. |pic_ci_status| image:: https://github.com/tsfpga/tsfpga/actions/workflows/ci.yml/badge.svg?branch=main
  :alt: CI status
  :target: https://github.com/tsfpga/tsfpga/actions/workflows/ci.yml

.. |pic_python_line_coverage| image:: https://tsfpga.com/badges/python_coverage.svg
  :alt: Python line coverage
  :target: https://tsfpga.com/python_coverage_html

|pic_website| |pic_repository| |pic_pip_install| |pic_license| |pic_chat| |pic_ci_status|
|pic_python_line_coverage|

tsfpga is a flexible and scalable development platform for modern FPGA projects.
With its Python-based build/simulation flow it is perfect for CI/CD and test-driven development.
The API is simple and easy to use
(a complete `simulation project <https://tsfpga.com/simulation.html>`__ is set up in less than
15 lines).

**See documentation on the website**: https://tsfpga.com

**Check out the source code on GitHub**: https://github.com/tsfpga/tsfpga

Key features
------------

* Source code-centric `project structure <https://tsfpga.com/module_structure.html>`__
  for scalability.
  Build projects, test configurations, constraints, IP cores, etc. are handled close to the
  source code, not in a central monolithic script.
* Automatically adds build/simulation sources if a recognized folder structure is used.
* Enables `local VUnit test configuration
  <https://tsfpga.com/simulation.html#local-configuration-of-test-cases>`__ without
  multiple ``run.py``.
* Handling of `IP cores <https://tsfpga.com/simulation.html#simulating-with-vivado-ip-cores>`__
  and `simlib <https://tsfpga.com/simulation.html#vivado-simulation-libraries>`__
  for your simulation project, with automatic re-compile when needed.
* Python-based `Vivado build system <https://tsfpga.com/fpga_build.html>`__ where many builds can
  be run in parallel.
* Tightly integrated with `hdl-registers <https://hdl-registers.com>`__.
  Register code generation is performed before each simulation and each build.
* Released under the very permissive BSD 3-Clause License.

The maintainers place high focus on quality, with everything having good unit test coverage and a
thought-out structure.
The project is mature and used in many production environments.

            

Raw data

            {
    "_id": null,
    "home_page": "",
    "name": "tsfpga",
    "maintainer": "",
    "docs_url": null,
    "requires_python": ">=3.9",
    "maintainer_email": "",
    "keywords": "asic,fpga,ci,simulation,test,vhdl,build-automation,eda,test-automation,rtl,verilog,xilinx,synthesis,vivado,systemverilog,implementation,vunit",
    "author": "Lukas Vik",
    "author_email": "10241915+LukasVik@users.noreply.github.com",
    "download_url": "https://files.pythonhosted.org/packages/0e/e3/0a41ec33eb27954e7d9f6c11f1a68cc32a799e06abf4cbfac0720dabdd64/tsfpga-12.3.1.tar.gz",
    "platform": null,
    "description": ".. image:: https://tsfpga.com/logos/banner.png\n  :alt: Project banner\n  :align: center\n\n|\n\n.. |pic_website| image:: https://tsfpga.com/badges/website.svg\n  :alt: Website\n  :target: https://tsfpga.com\n\n.. |pic_repository| image:: https://tsfpga.com/badges/repository.svg\n  :alt: Repository\n  :target: https://github.com/tsfpga/tsfpga\n\n.. |pic_chat| image:: https://tsfpga.com/badges/chat.svg\n  :alt: Chat\n  :target: https://github.com/tsfpga/tsfpga/discussions\n\n.. |pic_pip_install| image:: https://tsfpga.com/badges/pip_install.svg\n  :alt: pypi\n  :target: https://pypi.org/project/tsfpga/\n\n.. |pic_license| image:: https://tsfpga.com/badges/license.svg\n  :alt: License\n  :target: https://tsfpga.com/license_information.html\n\n.. |pic_ci_status| image:: https://github.com/tsfpga/tsfpga/actions/workflows/ci.yml/badge.svg?branch=main\n  :alt: CI status\n  :target: https://github.com/tsfpga/tsfpga/actions/workflows/ci.yml\n\n.. |pic_python_line_coverage| image:: https://tsfpga.com/badges/python_coverage.svg\n  :alt: Python line coverage\n  :target: https://tsfpga.com/python_coverage_html\n\n|pic_website| |pic_repository| |pic_pip_install| |pic_license| |pic_chat| |pic_ci_status|\n|pic_python_line_coverage|\n\ntsfpga is a flexible and scalable development platform for modern FPGA projects.\nWith its Python-based build/simulation flow it is perfect for CI/CD and test-driven development.\nThe API is simple and easy to use\n(a complete `simulation project <https://tsfpga.com/simulation.html>`__ is set up in less than\n15 lines).\n\n**See documentation on the website**: https://tsfpga.com\n\n**Check out the source code on GitHub**: https://github.com/tsfpga/tsfpga\n\nKey features\n------------\n\n* Source code-centric `project structure <https://tsfpga.com/module_structure.html>`__\n  for scalability.\n  Build projects, test configurations, constraints, IP cores, etc. are handled close to the\n  source code, not in a central monolithic script.\n* Automatically adds build/simulation sources if a recognized folder structure is used.\n* Enables `local VUnit test configuration\n  <https://tsfpga.com/simulation.html#local-configuration-of-test-cases>`__ without\n  multiple ``run.py``.\n* Handling of `IP cores <https://tsfpga.com/simulation.html#simulating-with-vivado-ip-cores>`__\n  and `simlib <https://tsfpga.com/simulation.html#vivado-simulation-libraries>`__\n  for your simulation project, with automatic re-compile when needed.\n* Python-based `Vivado build system <https://tsfpga.com/fpga_build.html>`__ where many builds can\n  be run in parallel.\n* Tightly integrated with `hdl-registers <https://hdl-registers.com>`__.\n  Register code generation is performed before each simulation and each build.\n* Released under the very permissive BSD 3-Clause License.\n\nThe maintainers place high focus on quality, with everything having good unit test coverage and a\nthought-out structure.\nThe project is mature and used in many production environments.\n",
    "bugtrack_url": null,
    "license": "BSD 3-Clause License",
    "summary": "A flexible and scalable development platform for modern FPGA projects",
    "version": "12.3.1",
    "project_urls": {
        "Changelog": "https://tsfpga.com/release_notes.html",
        "Documentation": "https://tsfpga.com",
        "Homepage": "https://tsfpga.com",
        "Issues": "https://github.com/tsfpga/tsfpga/issues",
        "Repository": "https://github.com/tsfpga/tsfpga"
    },
    "split_keywords": [
        "asic",
        "fpga",
        "ci",
        "simulation",
        "test",
        "vhdl",
        "build-automation",
        "eda",
        "test-automation",
        "rtl",
        "verilog",
        "xilinx",
        "synthesis",
        "vivado",
        "systemverilog",
        "implementation",
        "vunit"
    ],
    "urls": [
        {
            "comment_text": "",
            "digests": {
                "blake2b_256": "e339046e73d087c232715a51ab4efba51991cc215014069df7a357d2f7e202e2",
                "md5": "4e7dc75093655566aded0270a9209074",
                "sha256": "b3aa6b1304443c74aaaf76e4b37483ec9db780c85ebc1ca6bc5b485183f99840"
            },
            "downloads": -1,
            "filename": "tsfpga-12.3.1-py3-none-any.whl",
            "has_sig": false,
            "md5_digest": "4e7dc75093655566aded0270a9209074",
            "packagetype": "bdist_wheel",
            "python_version": "py3",
            "requires_python": ">=3.9",
            "size": 179884,
            "upload_time": "2024-03-08T09:33:32",
            "upload_time_iso_8601": "2024-03-08T09:33:32.443008Z",
            "url": "https://files.pythonhosted.org/packages/e3/39/046e73d087c232715a51ab4efba51991cc215014069df7a357d2f7e202e2/tsfpga-12.3.1-py3-none-any.whl",
            "yanked": false,
            "yanked_reason": null
        },
        {
            "comment_text": "",
            "digests": {
                "blake2b_256": "0ee30a41ec33eb27954e7d9f6c11f1a68cc32a799e06abf4cbfac0720dabdd64",
                "md5": "6a55770005fc19ed1a7f754857e56d5e",
                "sha256": "f10aeb8c048615aa1343a160e33e91e88adf1cc0f138e3a705041dfda83d09ef"
            },
            "downloads": -1,
            "filename": "tsfpga-12.3.1.tar.gz",
            "has_sig": false,
            "md5_digest": "6a55770005fc19ed1a7f754857e56d5e",
            "packagetype": "sdist",
            "python_version": "source",
            "requires_python": ">=3.9",
            "size": 127143,
            "upload_time": "2024-03-08T09:33:37",
            "upload_time_iso_8601": "2024-03-08T09:33:37.536221Z",
            "url": "https://files.pythonhosted.org/packages/0e/e3/0a41ec33eb27954e7d9f6c11f1a68cc32a799e06abf4cbfac0720dabdd64/tsfpga-12.3.1.tar.gz",
            "yanked": false,
            "yanked_reason": null
        }
    ],
    "upload_time": "2024-03-08 09:33:37",
    "github": true,
    "gitlab": false,
    "bitbucket": false,
    "codeberg": false,
    "github_user": "tsfpga",
    "github_project": "tsfpga",
    "travis_ci": false,
    "coveralls": false,
    "github_actions": true,
    "lcname": "tsfpga"
}
        
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