# VerilogPADAnalyzer
VerilogPAD is Python tool designed to analyze Verilog files, providing power, area, and delay metrics.
It is also released as a PyPi package under the name `verilog-pad-analyzer` (https://pypi.org/project/verilog-pad-analyzer/).
You may simply import it into your Python project by installing this package witht the command
```bash
$ pip install verilog-pad-analyzer
```
## Prerequisits
- Install the following tools:
1. **Python**
2. **Linux**
3. **Yosys**: link (https://github.com/YosysHQ/yosys)
4. **OpenSTA**: link (https://github.com/The-OpenROAD-Project/OpenSTA)
5. **Icarus Verilog**: link (https://github.com/steveicarus/iverilog)
**Note: add the binaries of 3, 4, and 5 to your PATH**
## Features
- **Comprehensive Analysis**: Compute detailed metrics for power consumption, physical area, and timing delay of Verilog circuits.
- **Intermediate File Handling**: Automatically manages intermediate files in a temporary directory to keep the workspace clean.
- **Report Generation**: Outputs analysis results in separate, organized report files for each metric.
## Folder Structure
- `./config/`: contains the technology library and synthesizer scripts
- `./src/`: contains the main classes and modules of the project
- `./VerilogPDA.py.temp/`: a temporary folder that is automatically created and stores the intermediate files such as synthesized files (can be safely removed afterward).
- `./VerilogPDA.py.report/`: a temporary folder that is automatically created and stores the area, power, and delay reports (can be safely removed afterward).
## Usage
To run the VerilogPADAnalyzer, use the following syntax:
### Arguments
```
$ python3 VerilogPDA.py [path-to-input]
```
For example, assuming that a circuit called `abs_diff_i4_o3.v` is located at the root directory, one can get the area, power, and delay reports of this circuit using the following command:
```
$ python3 VerilogPDA.py abs_diff_i4_o3.v
```
Upon launching the command above, three report files will be generated in `./VerilogPDA.py.report/` directory.
## Contributing
Contributions to the project are welcome. Please follow the standard GitHub pull request process to propose changes.
## Contact
For any inquiries or contributions, please contact Morteza at Rezaalipour.usi@gmail.com.
Raw data
{
"_id": null,
"home_page": "https://github.com/MortezaRezaalipour/VerilogPADAnalyzer",
"name": "verilog-pad-analyzer",
"maintainer": null,
"docs_url": null,
"requires_python": null,
"maintainer_email": null,
"keywords": "python, verilog, PAD, synthesis, analysis, circuit, EDA, simulation, hardware, design",
"author": "Morteza Rezaalipour (MorellRAP)",
"author_email": "<rezaalipour.usi@gmail.com>",
"download_url": "https://files.pythonhosted.org/packages/8c/84/274d58eb65002b4f5118fb8fe250f292144c3a62976e7e52680a95ee10ba/verilog_pad_analyzer-0.0.7.tar.gz",
"platform": null,
"description": "# VerilogPADAnalyzer\n\nVerilogPAD is Python tool designed to analyze Verilog files, providing power, area, and delay metrics.\nIt is also released as a PyPi package under the name `verilog-pad-analyzer` (https://pypi.org/project/verilog-pad-analyzer/). \n\nYou may simply import it into your Python project by installing this package witht the command \n\n```bash \n$ pip install verilog-pad-analyzer\n```\n\n\n## Prerequisits\n- Install the following tools:\n1. **Python**\n2. **Linux**\n3. **Yosys**: link (https://github.com/YosysHQ/yosys)\n4. **OpenSTA**: link (https://github.com/The-OpenROAD-Project/OpenSTA)\n5. **Icarus Verilog**: link (https://github.com/steveicarus/iverilog)\n\n**Note: add the binaries of 3, 4, and 5 to your PATH**\n\n## Features\n- **Comprehensive Analysis**: Compute detailed metrics for power consumption, physical area, and timing delay of Verilog circuits.\n- **Intermediate File Handling**: Automatically manages intermediate files in a temporary directory to keep the workspace clean.\n- **Report Generation**: Outputs analysis results in separate, organized report files for each metric.\n\n\n## Folder Structure\n- `./config/`: contains the technology library and synthesizer scripts\n- `./src/`: contains the main classes and modules of the project\n- `./VerilogPDA.py.temp/`: a temporary folder that is automatically created and stores the intermediate files such as synthesized files (can be safely removed afterward).\n- `./VerilogPDA.py.report/`: a temporary folder that is automatically created and stores the area, power, and delay reports (can be safely removed afterward).\n\n## Usage\n\nTo run the VerilogPADAnalyzer, use the following syntax:\n\n\n\n### Arguments\n\n```\n$ python3 VerilogPDA.py [path-to-input]\n```\nFor example, assuming that a circuit called `abs_diff_i4_o3.v` is located at the root directory, one can get the area, power, and delay reports of this circuit using the following command: \n\n```\n$ python3 VerilogPDA.py abs_diff_i4_o3.v\n```\nUpon launching the command above, three report files will be generated in `./VerilogPDA.py.report/` directory. \n\n\n## Contributing\nContributions to the project are welcome. Please follow the standard GitHub pull request process to propose changes.\n\n\n## Contact\nFor any inquiries or contributions, please contact Morteza at Rezaalipour.usi@gmail.com.\n",
"bugtrack_url": null,
"license": null,
"summary": "VerilogPADAnalyzer is a Python application designed to analyze and report the",
"version": "0.0.7",
"project_urls": {
"Homepage": "https://github.com/MortezaRezaalipour/VerilogPADAnalyzer"
},
"split_keywords": [
"python",
" verilog",
" pad",
" synthesis",
" analysis",
" circuit",
" eda",
" simulation",
" hardware",
" design"
],
"urls": [
{
"comment_text": "",
"digests": {
"blake2b_256": "818cb3c3a3520494f7849f8f6149242195959c2e0aec3bb00c9bbb6cebdc4903",
"md5": "6c0a2fd7a78bb549c3494b668a6507aa",
"sha256": "918fc580f9f0f9318f52c7ed4b25c797addc69dca7b0eba39e6e865f735287a1"
},
"downloads": -1,
"filename": "verilog_pad_analyzer-0.0.7-py3-none-any.whl",
"has_sig": false,
"md5_digest": "6c0a2fd7a78bb549c3494b668a6507aa",
"packagetype": "bdist_wheel",
"python_version": "py3",
"requires_python": null,
"size": 80647,
"upload_time": "2024-11-21T07:02:38",
"upload_time_iso_8601": "2024-11-21T07:02:38.073680Z",
"url": "https://files.pythonhosted.org/packages/81/8c/b3c3a3520494f7849f8f6149242195959c2e0aec3bb00c9bbb6cebdc4903/verilog_pad_analyzer-0.0.7-py3-none-any.whl",
"yanked": false,
"yanked_reason": null
},
{
"comment_text": "",
"digests": {
"blake2b_256": "8c84274d58eb65002b4f5118fb8fe250f292144c3a62976e7e52680a95ee10ba",
"md5": "7b41288579ac1920ad8ffb029278cc29",
"sha256": "203b597f250a59d4d362de6c6861090fc0561e4fd256346a8fd1076881340d58"
},
"downloads": -1,
"filename": "verilog_pad_analyzer-0.0.7.tar.gz",
"has_sig": false,
"md5_digest": "7b41288579ac1920ad8ffb029278cc29",
"packagetype": "sdist",
"python_version": "source",
"requires_python": null,
"size": 79545,
"upload_time": "2024-11-21T07:02:39",
"upload_time_iso_8601": "2024-11-21T07:02:39.644074Z",
"url": "https://files.pythonhosted.org/packages/8c/84/274d58eb65002b4f5118fb8fe250f292144c3a62976e7e52680a95ee10ba/verilog_pad_analyzer-0.0.7.tar.gz",
"yanked": false,
"yanked_reason": null
}
],
"upload_time": "2024-11-21 07:02:39",
"github": true,
"gitlab": false,
"bitbucket": false,
"codeberg": false,
"github_user": "MortezaRezaalipour",
"github_project": "VerilogPADAnalyzer",
"travis_ci": false,
"coveralls": false,
"github_actions": true,
"lcname": "verilog-pad-analyzer"
}
JSON
