verilog-parser

Name	verilog-parser JSON
Version	0.0.5 JSON
	download
home_page	None
Summary	Parser for structural verilog.
upload_time	2024-11-20 10:13:07
maintainer	None
docs_url	None
author	None
requires_python	>=3.7
license	AGPL-3.0-or-later
keywords	verilog parser
VCS
bugtrack_url
requirements	No requirements were recorded.
Travis-CI	No Travis.
coveralls test coverage	No coveralls.

            # Verilog parser for Python
Lark based parser for Verilog netlists (structural Verilog without behavioral statements).
This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.

## Example
```python
from verilog_parser.parser import parse_verilog
ast = parse_verilog(open(verilog_file_path).read())
```

## Install

From PyPI:
```sh
pip install verilog-parser
```

From git:
```sh
pip install git+https://codeberg.org/tok/py-verilog-parser
```

From git for development:
```sh
git clone https://codeberg.org/tok/py-verilog-parser
cd py-verilog-parser
pip install --editable .
```


            

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