Veriloggen
==============================
[](https://github.com/PyHDI/veriloggen/actions/workflows/main.yml)
[](https://www.travis-ci.com/PyHDI/veriloggen)
A Mixed-Paradigm Hardware Construction Framework
Copyright 2015, Shinya Takamaeda-Yamazaki and Contributors
License
==============================
Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
Publication
==============================
If you use Veriloggen in your research, please cite my paper about Pyverilog. (Veriloggen is constructed on Pyverilog.)
- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015.
[Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42)
```
@inproceedings{Takamaeda:2015:ARC:Pyverilog,
title={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},
author={Takamaeda-Yamazaki, Shinya},
booktitle={Applied Reconfigurable Computing},
month={Apr},
year={2015},
pages={451-460},
volume={9040},
series={Lecture Notes in Computer Science},
publisher={Springer International Publishing},
doi={10.1007/978-3-319-16214-0_42},
url={http://dx.doi.org/10.1007/978-3-319-16214-0_42},
}
```
What's Veriloggen?
==============================
Veriloggen is a mixed-paradigm framework for constructing a hardware in Python.
Veriloggen provides a low-level abstraction of Verilog HDL AST. You can build up a hardware design written in Verilog HDL very easily by using the AST abstraction and the entire functionality of Python.
In addition to the low-level abstraction of Verilog HDL, Veriloggen provides high-level abstractions to productively express a hardware structure.
- **Stream** is a dataflow-based high-level synthesis layer for high-performance parallel stream processing.
- **Thread** is a procedural high-level synthesis layer to express sequential behaviors, such as DMA transfers and controls.
Veriloggen is not designed for designing a hardware by programmer directly, but is for providing an efficient abstraction to develop a more efficient domain specific language and tools.
Contribute to Veriloggen
==============================
Veriloggen project always welcomes questions, bug reports, feature proposals, and pull requests on [GitHub](https://github.com/PyHDI/veriloggen).
for questions, bug reports, and feature proposals
--------------------
Please leave your comment on the [issue tracker](https://github.com/PyHDI/veriloggen/issues) on GitHub.
for pull requests
--------------------
Please check "CONTRIBUTORS.md" for the contributors who provided pull requests.
Veriloggen uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**
To write a testing code, please refer the existing testing examples in "tests" directory.
If the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the *develop* branch by the main committers.
Installation
==============================
Requirements
--------------------
- Python: 3.7.7 or later
- Python 3.9.5 (via pyenv) is recommended for macOS with Apple Silicon.
- Icarus Verilog: 10.1 or later
```
sudo apt install iverilog
```
- pyverilog: 1.3.0 or later
- pyverilog requires Jinja2. Jinja2 3.0.3 is recommended for macOS with Apple Silicon.
- numpy: 1.17 or later
- numpy 1.22.1 is recommended for macOS with Apple Silicon.
```
pip3 install pyverilog numpy
```
Optional installation for testing
--------------------
These are required for automatic testing of **tests** and **examples**.
We recommend to install these testing library to verify experimental features.
- pytest: 3.8.1 or later
- pytest-pythonpath: 0.7.3 or later
```
pip3 install pytest pytest-pythonpath
```
For fast RTL simulation, we recommend to install Verilator.
- Verilator: 4.028 or later
```
sudo apt install verilator
```
Optional installation for visualization
--------------------
To visualize the generated hardware by veriloggen.stream, these libraries are required.
- graphviz: 2.38.0 or later
- pygraphviz: 1.3.1 or later
```
sudo apt install graphviz
pip3 install pygraphviz
```
Install
--------------------
Now you can install Veriloggen using setup.py script:
```
python3 setup.py install
```
Docker
--------------------
Dockerfile is available. You can try Veriloggen on Docker without any installation on your host platform.
```
cd docker
sudo docker build -t user/veriloggen .
sudo docker run --name veriloggen -i -t user/veriloggen /bin/bash
cd veriloggen/examples/led/
make
```
Examples and testing
==============================
There are some exapmles in **examples** and various testing codes in **tests**.
The testing codes are actually good small examples suggesting how to represent a desired function.
To run the testing codes, please type the following commands.
```
cd tests
python3 -m pytest .
```
If you use Verilator instead of Icarus Verilog for RTL simulation, set "--sim" option.
```
python3 -m pytest --sim=verilator .
```
Getting started
==============================
You can find some examples in 'veriloggen/examples/' and 'veriloggen/tests'.
Let's begin veriloggen by an example. Create a example Python script in Python as below. A blinking LED hardware is modeled in Python.
Open 'hello_led.py' in the root directory.
```python
from __future__ import absolute_import
from __future__ import print_function
import sys
import os
from veriloggen import *
def mkLed():
m = Module('blinkled')
width = m.Parameter('WIDTH', 8)
clk = m.Input('CLK')
rst = m.Input('RST')
led = m.OutputReg('LED', width, initval=0)
count = m.Reg('count', 32, initval=0)
seq = Seq(m, 'seq', clk, rst)
seq.If(count == 1024 - 1)(
count(0)
).Else(
count.inc()
)
seq.If(count == 1024 - 1)(
led.inc()
)
seq(
Systask('display', "LED:%d count:%d", led, count)
)
return m
def mkTest():
m = Module('test')
# target instance
led = mkLed()
uut = Submodule(m, led, name='uut')
clk = uut['CLK']
rst = uut['RST']
simulation.setup_waveform(m, uut, m.get_vars())
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
init.add(
Delay(1000 * 100),
Systask('finish'),
)
return m
if __name__ == '__main__':
test = mkTest()
verilog = test.to_verilog(filename='tmp.v')
#verilog = test.to_verilog()
print(verilog)
sim = simulation.Simulator(test)
rslt = sim.run()
print(rslt)
# sim.view_waveform()
```
Run the script.
```
python3 hello_led.py
```
You will have a complete Verilog HDL source code named 'tmp.v' as below, which is generated by the source code generator.
```verilog
module test
(
);
localparam uut_WIDTH = 8;
reg uut_CLK;
reg uut_RST;
wire [uut_WIDTH-1:0] uut_LED;
blinkled
uut
(
.CLK(uut_CLK),
.RST(uut_RST),
.LED(uut_LED)
);
initial begin
$dumpfile("uut.vcd");
$dumpvars(0, uut, uut_CLK, uut_RST, uut_LED);
end
initial begin
uut_CLK = 0;
forever begin
#5 uut_CLK = !uut_CLK;
end
end
initial begin
uut_RST = 0;
#100;
uut_RST = 1;
#100;
uut_RST = 0;
#100000;
$finish;
end
endmodule
module blinkled #
(
parameter WIDTH = 8
)
(
input CLK,
input RST,
output reg [WIDTH-1:0] LED
);
reg [32-1:0] count;
always @(posedge CLK) begin
if(RST) begin
count <= 0;
LED <= 0;
end else begin
if(count == 1023) begin
count <= 0;
end else begin
count <= count + 1;
end
if(count == 1023) begin
LED <= LED + 1;
end
$display("LED:%d count:%d", LED, count);
end
end
endmodule
```
You will also see the simulation result of the generated Verilog code on Icarus Verilog.
```
VCD info: dumpfile uut.vcd opened for output.
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: x count: x
LED: 0 count: 0
LED: 0 count: 1
LED: 0 count: 2
LED: 0 count: 3
LED: 0 count: 4
...
LED: 9 count: 777
LED: 9 count: 778
LED: 9 count: 779
LED: 9 count: 780
LED: 9 count: 781
LED: 9 count: 782
LED: 9 count: 783
```
If you installed GTKwave and enable 'sim.view_waveform()' in 'hello_led.py', you can see the waveform the simulation result.
Veriloggen extension libraries
==============================
Mixed-paradigm high-level synthesis
--------------------
- veriloggen.thread.Thread: Procedural high-level synthesis for DMA and I/O controls
- veriloggen.thread.Stream: Dataflow-based high-level synthesis for high-performance stream processing
Frequently-used abstractions
--------------------
- veriloggen.verilog: Verilog HDL source code synthesis and import APIs
- veriloggen.simulation: Simulation APIs via Verilog simulators
- veriloggen.seq: Synchronous circuit builder (Seq)
- veriloggen.fsm: Finite state machine builder (FSM)
Please see examples and tests directories for many examples.
Related project
==============================
[Pyverilog](https://github.com/PyHDI/Pyverilog)
- Python-based Hardware Design Processing Toolkit for Verilog HDL
[NNgen](https://github.com/NNgen/nngen)
- A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
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"description": "Veriloggen\n==============================\n\n[](https://github.com/PyHDI/veriloggen/actions/workflows/main.yml)\n[](https://www.travis-ci.com/PyHDI/veriloggen)\n\nA Mixed-Paradigm Hardware Construction Framework\n\nCopyright 2015, Shinya Takamaeda-Yamazaki and Contributors\n\n\nLicense\n==============================\n\nApache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)\n\n\nPublication\n==============================\n\nIf you use Veriloggen in your research, please cite my paper about Pyverilog. (Veriloggen is constructed on Pyverilog.)\n\n- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015.\n[Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42)\n\n```\n@inproceedings{Takamaeda:2015:ARC:Pyverilog,\ntitle={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},\nauthor={Takamaeda-Yamazaki, Shinya},\nbooktitle={Applied Reconfigurable Computing},\nmonth={Apr},\nyear={2015},\npages={451-460},\nvolume={9040},\nseries={Lecture Notes in Computer Science},\npublisher={Springer International Publishing},\ndoi={10.1007/978-3-319-16214-0_42},\nurl={http://dx.doi.org/10.1007/978-3-319-16214-0_42},\n}\n```\n\n\nWhat's Veriloggen?\n==============================\n\nVeriloggen is a mixed-paradigm framework for constructing a hardware in Python.\n\nVeriloggen provides a low-level abstraction of Verilog HDL AST. You can build up a hardware design written in Verilog HDL very easily by using the AST abstraction and the entire functionality of Python.\n\nIn addition to the low-level abstraction of Verilog HDL, Veriloggen provides high-level abstractions to productively express a hardware structure.\n\n- **Stream** is a dataflow-based high-level synthesis layer for high-performance parallel stream processing.\n- **Thread** is a procedural high-level synthesis layer to express sequential behaviors, such as DMA transfers and controls.\n\nVeriloggen is not designed for designing a hardware by programmer directly, but is for providing an efficient abstraction to develop a more efficient domain specific language and tools.\n\n\nContribute to Veriloggen\n==============================\n\nVeriloggen project always welcomes questions, bug reports, feature proposals, and pull requests on [GitHub](https://github.com/PyHDI/veriloggen).\n\nfor questions, bug reports, and feature proposals\n--------------------\n\nPlease leave your comment on the [issue tracker](https://github.com/PyHDI/veriloggen/issues) on GitHub.\n\nfor pull requests\n--------------------\n\nPlease check \"CONTRIBUTORS.md\" for the contributors who provided pull requests.\n\nVeriloggen uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**\nTo write a testing code, please refer the existing testing examples in \"tests\" directory.\n\nIf the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the *develop* branch by the main committers.\n\n\nInstallation\n==============================\n\nRequirements\n--------------------\n\n- Python: 3.7.7 or later\n - Python 3.9.5 (via pyenv) is recommended for macOS with Apple Silicon.\n- Icarus Verilog: 10.1 or later\n\n```\nsudo apt install iverilog\n```\n\n- pyverilog: 1.3.0 or later\n - pyverilog requires Jinja2. Jinja2 3.0.3 is recommended for macOS with Apple Silicon.\n- numpy: 1.17 or later\n - numpy 1.22.1 is recommended for macOS with Apple Silicon.\n\n```\npip3 install pyverilog numpy\n```\n\nOptional installation for testing\n--------------------\n\nThese are required for automatic testing of **tests** and **examples**.\nWe recommend to install these testing library to verify experimental features.\n\n- pytest: 3.8.1 or later\n- pytest-pythonpath: 0.7.3 or later\n\n```\npip3 install pytest pytest-pythonpath\n```\n\nFor fast RTL simulation, we recommend to install Verilator.\n\n- Verilator: 4.028 or later\n\n```\nsudo apt install verilator\n```\n\nOptional installation for visualization\n--------------------\n\nTo visualize the generated hardware by veriloggen.stream, these libraries are required.\n\n- graphviz: 2.38.0 or later\n- pygraphviz: 1.3.1 or later\n\n```\nsudo apt install graphviz\npip3 install pygraphviz\n```\n\nInstall\n--------------------\n\nNow you can install Veriloggen using setup.py script:\n\n```\npython3 setup.py install\n```\n\nDocker\n--------------------\n\nDockerfile is available. You can try Veriloggen on Docker without any installation on your host platform.\n\n```\ncd docker\nsudo docker build -t user/veriloggen .\nsudo docker run --name veriloggen -i -t user/veriloggen /bin/bash\ncd veriloggen/examples/led/\nmake\n```\n\n\nExamples and testing\n==============================\n\nThere are some exapmles in **examples** and various testing codes in **tests**.\nThe testing codes are actually good small examples suggesting how to represent a desired function.\n\nTo run the testing codes, please type the following commands.\n\n```\ncd tests\npython3 -m pytest .\n```\n\nIf you use Verilator instead of Icarus Verilog for RTL simulation, set \"--sim\" option.\n\n```\npython3 -m pytest --sim=verilator .\n```\n\n\nGetting started\n==============================\n\nYou can find some examples in 'veriloggen/examples/' and 'veriloggen/tests'.\n\nLet's begin veriloggen by an example. Create a example Python script in Python as below. A blinking LED hardware is modeled in Python.\nOpen 'hello_led.py' in the root directory.\n\n```python\nfrom __future__ import absolute_import\nfrom __future__ import print_function\nimport sys\nimport os\nfrom veriloggen import *\n\n\ndef mkLed():\n m = Module('blinkled')\n width = m.Parameter('WIDTH', 8)\n clk = m.Input('CLK')\n rst = m.Input('RST')\n led = m.OutputReg('LED', width, initval=0)\n count = m.Reg('count', 32, initval=0)\n\n seq = Seq(m, 'seq', clk, rst)\n\n seq.If(count == 1024 - 1)(\n count(0)\n ).Else(\n count.inc()\n )\n\n seq.If(count == 1024 - 1)(\n led.inc()\n )\n\n seq(\n Systask('display', \"LED:%d count:%d\", led, count)\n )\n\n return m\n\n\ndef mkTest():\n m = Module('test')\n\n # target instance\n led = mkLed()\n\n uut = Submodule(m, led, name='uut')\n clk = uut['CLK']\n rst = uut['RST']\n\n simulation.setup_waveform(m, uut, m.get_vars())\n simulation.setup_clock(m, clk, hperiod=5)\n init = simulation.setup_reset(m, rst, m.make_reset(), period=100)\n\n init.add(\n Delay(1000 * 100),\n Systask('finish'),\n )\n\n return m\n\nif __name__ == '__main__':\n test = mkTest()\n verilog = test.to_verilog(filename='tmp.v')\n #verilog = test.to_verilog()\n print(verilog)\n\n sim = simulation.Simulator(test)\n rslt = sim.run()\n print(rslt)\n\n # sim.view_waveform()\n```\n\nRun the script.\n\n```\npython3 hello_led.py\n```\n\nYou will have a complete Verilog HDL source code named 'tmp.v' as below, which is generated by the source code generator.\n\n```verilog\nmodule test\n(\n\n);\n\n localparam uut_WIDTH = 8;\n reg uut_CLK;\n reg uut_RST;\n wire [uut_WIDTH-1:0] uut_LED;\n\n blinkled\n uut\n (\n .CLK(uut_CLK),\n .RST(uut_RST),\n .LED(uut_LED)\n );\n\n\n initial begin\n $dumpfile(\"uut.vcd\");\n $dumpvars(0, uut, uut_CLK, uut_RST, uut_LED);\n end\n\n\n initial begin\n uut_CLK = 0;\n forever begin\n #5 uut_CLK = !uut_CLK;\n end\n end\n\n\n initial begin\n uut_RST = 0;\n #100;\n uut_RST = 1;\n #100;\n uut_RST = 0;\n #100000;\n $finish;\n end\n\n\nendmodule\n\n\n\nmodule blinkled #\n(\n parameter WIDTH = 8\n)\n(\n input CLK,\n input RST,\n output reg [WIDTH-1:0] LED\n);\n\n reg [32-1:0] count;\n\n always @(posedge CLK) begin\n if(RST) begin\n count <= 0;\n LED <= 0;\n end else begin\n if(count == 1023) begin\n count <= 0;\n end else begin\n count <= count + 1;\n end\n if(count == 1023) begin\n LED <= LED + 1;\n end \n $display(\"LED:%d count:%d\", LED, count);\n end\n end\n\n\nendmodule\n```\n\nYou will also see the simulation result of the generated Verilog code on Icarus Verilog.\n\n```\nVCD info: dumpfile uut.vcd opened for output.\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: x count: x\nLED: 0 count: 0\nLED: 0 count: 1\nLED: 0 count: 2\nLED: 0 count: 3\nLED: 0 count: 4\n...\nLED: 9 count: 777\nLED: 9 count: 778\nLED: 9 count: 779\nLED: 9 count: 780\nLED: 9 count: 781\nLED: 9 count: 782\nLED: 9 count: 783\n```\n\nIf you installed GTKwave and enable 'sim.view_waveform()' in 'hello_led.py', you can see the waveform the simulation result.\n\n\n\n\nVeriloggen extension libraries\n==============================\n\nMixed-paradigm high-level synthesis\n--------------------\n\n- veriloggen.thread.Thread: Procedural high-level synthesis for DMA and I/O controls\n- veriloggen.thread.Stream: Dataflow-based high-level synthesis for high-performance stream processing\n\nFrequently-used abstractions\n--------------------\n\n- veriloggen.verilog: Verilog HDL source code synthesis and import APIs\n- veriloggen.simulation: Simulation APIs via Verilog simulators\n- veriloggen.seq: Synchronous circuit builder (Seq)\n- veriloggen.fsm: Finite state machine builder (FSM)\n\nPlease see examples and tests directories for many examples.\n\n\nRelated project\n==============================\n\n[Pyverilog](https://github.com/PyHDI/Pyverilog)\n- Python-based Hardware Design Processing Toolkit for Verilog HDL\n\n[NNgen](https://github.com/NNgen/nngen)\n- A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network\n",
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