| Name | Version | Summary | date |
|---|---|---|---|
| zuspec-be-sw | 0.0.1.6503696132 | Backend library to generate software output | 2023-10-13 03:38:09 |
| sphinxcontrib-hdl-diagrams | 0.0.post160 | Generate diagrams from HDL in Sphinx. | 2023-09-21 05:39:48 |
| aide-core | 1.0.1000 | A professional collaborative platform for embedded development. Cross-platform IDE and Unified Debugger. Static Code Analyzer and Remote Unit Testing. Multi-platform and Multi-architecture Build System. Firmware File Explorer and Memory Inspection. IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbedOS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V, STMicroelectronics (STM8/STM32), Teensy | 2023-08-29 14:17:47 |
| pySVModel | 0.4.1 | An abstract SystemVerilog language model (incl. Verilog). | 2023-08-15 22:19:34 |
| xeda | 0.2.5 | Cross EDA Abstraction and Automation | 2023-07-26 17:38:36 |
| ipsocgen | 0.1.39 | Generic SoC builder in HDL | 2023-06-24 22:45:09 |
| dovado-rtl | 0.10.11 | RTL Design Space Exploration on top of Vivado | 2023-04-28 08:23:25 |
| fusesoc | 2.2.1 | FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code. | 2023-04-24 13:27:02 |
| uvm-python | 0.3.0 | uvm-python UVM implementation in Python on top of cocotb | 2023-03-29 17:07:48 |
| morell-test-attempt-verilog | 0.0.2 | A Verilog Class | 2023-03-19 08:15:47 |
| morellsecondverpackage | 0.0.1 | A Verilog Class | 2023-03-18 07:34:54 |
| morell-verilog-class | 0.0.1 | A Verilog Class | 2023-03-18 06:22:34 |
| libarl | 0.0.1.3625797450 | Core ARL model evaluator library | 2022-12-06 02:24:00 |
| libvsc | 0.0.1.3615208868 | Core Verification Stimulus and Coverage library | 2022-12-04 21:50:55 |
| PyVerilator | 0.7.0 | Python interface to Verilator models | 2021-05-20 18:27:29 |
| hour | day | week | total |
|---|---|---|---|
| 35 | 1918 | 10303 | 201599 |