hdl-parser


Namehdl-parser JSON
Version 1.0.1 PyPI version JSON
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home_pageNone
SummaryEasy-To-Use SystemVerilog Parser
upload_time2025-09-08 13:41:45
maintainerNone
docs_urlNone
authorNone
requires_python<4.0,>=3.10.0
licenseNone
keywords systemverilog verilog parser
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coveralls test coverage No coveralls.
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# Easy-To-Use SystemVerilog Parser

* [Documentation](https://hdl-parser.readthedocs.io/en/stable/)
* [PyPI](https://pypi.org/project/hdl-parser/)
* [Sources](https://github.com/ericsmacedo/hdl-parser)
* [Issues](https://github.com/ericsmacedo/hdl-parser/issues)

## Features

* Extract Port Lists
* Extract Parameters
* Extract Submodule Instances and their connections
* `ifdef` support
* Standards: `IEEE 1800-2009 SystemVerilog`

## Limitations

* **No Syntax Checks** - Source Code files must be syntactically correct
* **No Full Parser** - This parser intends to be simple and just extract some information from the source code. **Fast and Simple.**

## Installation

Installing it is pretty easy:

```bash
pip install hdl-parser
```

## Authors

* [Eric Macedo](mailto:ericsmacedo@gmail.com)
* [Daniel Jakschik](mailto:iccode17@gmail.com)

## Usage

See [Usage Documentation](https://hdl-parser.readthedocs.io/en/stable/usage/)

            

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