peakrdl-regblock

Name	peakrdl-regblock JSON
Version	0.23.0 JSON
	download
home_page	None
Summary	Compile SystemRDL into a SystemVerilog control/status register (CSR) block
upload_time	2024-12-20 06:06:20
maintainer	None
docs_url	None
author	Alex Mykyta
requires_python	>=3.6
license	GPLv3
keywords	systemrdl peakrdl csr compiler tool registers generator verilog systemverilog register abstraction layer fpga asic
VCS
bugtrack_url
requirements	No requirements were recorded.
Travis-CI	No Travis.
coveralls test coverage	No coveralls.

            [![Documentation Status](https://readthedocs.org/projects/peakrdl-regblock/badge/?version=latest)](http://peakrdl-regblock.readthedocs.io)
[![build](https://github.com/SystemRDL/PeakRDL-regblock/workflows/build/badge.svg)](https://github.com/SystemRDL/PeakRDL-regblock/actions?query=workflow%3Abuild+branch%3Amain)
[![Coverage Status](https://coveralls.io/repos/github/SystemRDL/PeakRDL-regblock/badge.svg?branch=main)](https://coveralls.io/github/SystemRDL/PeakRDL-regblock?branch=main)
[![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock)

# PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the [PeakRDL project](https://peakrdl.readthedocs.io).

## Documentation
See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details

            

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