| Name | Version | Summary | date |
| peakrdl-viz |
1.0.1 |
Generate visualization code for MakerChip VIZ framework. |
2025-07-16 13:35:38 |
| peakrdl-python |
1.2.0 |
Generate Python Register Access Layer (RAL) from SystemRDL |
2025-04-25 13:37:47 |
| systemrdl-compiler |
1.29.3 |
Parse and elaborate front-end for SystemRDL 2.0 |
2025-01-09 03:58:59 |
| peakrdl-regblock |
0.23.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-12-20 06:06:20 |
| peakrdl |
1.2.3 |
Toolchain for control/status register automation and code generation. |
2024-12-17 06:42:29 |
| peakrdl-cli |
1.2.3 |
Command-line tool for control/status register automation and code generation. |
2024-12-17 06:41:36 |
| pySystemRDLModel |
0.3.2 |
An abstract SystemRDL language model. |
2024-11-11 23:53:17 |
| peakrdl-ipxact |
3.5.0 |
Import and export IP-XACT XML to/from the systemrdl-compiler register model |
2024-10-15 04:45:01 |
| peakrdl-docx |
0.4.7 |
Compile SystemRDL definition into a Docx (MsWord) document |
2024-09-19 08:54:40 |
| peakrdl-beam |
0.1.0 |
Generate Erlang or Elixir modules from a SystemRDL register model |
2024-08-02 14:53:16 |
| peakrdl-sv |
0.0.1 |
A SystemRDL exporter for SystemVerilog |
2024-03-07 11:54:22 |
| desyrdl |
1.3.0 |
DesyRDL - Tool for address space and register generation |
2024-01-04 09:37:54 |