| Name | Version | Summary | date |
|---|---|---|---|
| peakrdl-python | 0.7.4 | Generate Python Register Access Layer (RAL) from SystemRDL | 2024-04-02 13:26:09 |
| peakrdl-regblock | 0.22.0 | Compile SystemRDL into a SystemVerilog control/status register (CSR) block | 2024-04-01 05:27:07 |
| peakrdl-ipxact | 3.4.4 | Import and export IP-XACT XML to/from the systemrdl-compiler register model | 2024-03-30 06:04:08 |
| peakrdl-sv | 0.0.1 | A SystemRDL exporter for SystemVerilog | 2024-03-07 11:54:22 |
| desyrdl | 1.3.0 | DesyRDL - Tool for address space and register generation | 2024-01-04 09:37:54 |
| pySystemRDLModel | 0.2.2 | An abstract SystemRDL language model. | 2023-08-15 22:30:08 |
| hour | day | week | total |
|---|---|---|---|
| 78 | 2318 | 9895 | 205442 |