# peakrdl-sv
This SystemRDL exporter outputs SystemVerilog that is hopefully consumable by *any*
EDA tool including the common open source simulators such as Icarus and Verilator.
The design philosophy was to keep it simple and avoid the complexity of implementing
the full SystemRDL language. As such there are limitations on what is supported and
there are no plans to extend support beyond the basics.
## Alternatives
There are already many Verilog SystemRDL exporters out there including `PeakRDL-regblock`
which is maintained by the author of many of the Python tooling.
### PeakRDL-regblock
This is probably the most fully featured of the Verilog/SV exporters but it generates
SV that can't be consumed by all tools. There is a definite verification style to the
RTL with the use of unpacked structs, interfaces, automatic variables etc.
Additionally, the code base is so complex that it took less time to implement an exporter
from scratch than to try and fix the issues.
If you need support for the majority of the SystemRDL features and have commercial EDA
tools then I'd suggest looking at this package.
### PeakRDL-verilog
There are two GitHub repos that use this name. The original author has mostly abandonned
their own work in favour of `PeakRDL-regblock` while his work was forked and continues (?)
to be maintained here: https://github.com/bat52/PeakRDL-verilog
Both have simple to fix bugs relating to recent versions of Python but the latter project
has not enabled issues so further investigation was ruled out.
### OpenTitan RegTool
Perhaps the nicest and cleanest register tool out there is `RegTool`. This is part of the
open source OpenTitan project and you can find the documentation here:
https://opentitan.org/book/util/reggen/index.html
The tool uses its own HJSON schema to define the registers and is somewhat simpler than
SystemRDL. However, as it has matured, the tooling has become more and more deeply
embedded in the OT workflows with requirements for metadata driven from the IP blocks
that use it. Extracting a generic version of this tool would be a major undertaking and
importing the Python tooling into your own project isn't clean.
On the plus side, the RTL generated is very clean with a module hierarchy that simplifies
the work needed on the Python side.
## Implementation Details
The implementation choices were made to simplify the complexity of the Python RDL
exporter. Rather than generating a flat RTL view of the whole register file, as is
done by many of the current SystemRDL exporters, each field is instantiated as a
parameterisable Verilog module. This vastly reduces the complexity of both the
templating and the exporter code by moving specialisation into the RTL via generate
statements.
This also happened to be the approach taken by `RegTool` which meant that much of the RTL
infrastructure could be taken and modified without much overhead. There is a very clear
lineage from the OpenTitan work in this exporter in both the RTL and Mako templating.
### RTL Hierarchy
REVISIT: flesh out this section.
The hierarchy of the generated RTL is shown below:
+---- <block>_reg_pkg
|
+---- <block>_reg_top
|
+---- rdl_subreg u_field_name_0
| |
| +---- rdl_subreg_arg u_arb
| |
| +---- rdl_subreg_flop u_flop
|
+---- rdl_subreg u_field_name_1
| |
| +---- rdl_subreg_arg u_arb
| |
| +---- rdl_subreg_flop u_flop
|
+---- rdl_subreg u_field_name_2
|
...
## Installation
```
$ pip install git+https://github.com/nuquantum/peakrdl-sv
```
## Usage
The exporter integrates with PeakRDL via the plugin flow defined here:
https://peakrdl.readthedocs.io/en/latest/for-devs/exporter-plugin.html
```
$ peakrdl sv -o ./generated <filename.rdl>
```
You can also run a standalone script that offers both `export` and `install`
targets. The latter will install the required RTL dependencies to a local directory.
This can also be done at the `export` stage by passing the `--include-subreg` argument.
```
$ sv-exporter -h
usage: sv-exporter [-h] [-v] [-o OUTPUT] {export,install} ...
positional arguments:
{export,install}
export Run the SystemVerlog RDL exporter
install Install SV source files into local tree
options:
-h, --help show this help message and exit
-v, --verbose Enable verbose logging
-o OUTPUT, --output OUTPUT
Specify the output path
$ sv-exporter -o ./rtl install
$ sv-exporter -0 ./rtl export <filename>.rdl
$ sv-exporter -0 ./rtl export --include-subreg <filename>.rdl
```
## Limitations
The following is a list of current limitations and assumptions:
* there is a single toplevel address map
* only support for a single sw access width
* no support for register widths > access width
* no support for countrs
* no support for aliases
* no support for interrupt registers
* no support for halt registers
* no support for swacc
* no support for onread side effects
Raw data
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"description": "# peakrdl-sv\n\nThis SystemRDL exporter outputs SystemVerilog that is hopefully consumable by *any* \nEDA tool including the common open source simulators such as Icarus and Verilator.\n\nThe design philosophy was to keep it simple and avoid the complexity of implementing\nthe full SystemRDL language. As such there are limitations on what is supported and\nthere are no plans to extend support beyond the basics.\n\n## Alternatives\n\nThere are already many Verilog SystemRDL exporters out there including `PeakRDL-regblock` \nwhich is maintained by the author of many of the Python tooling.\n\n### PeakRDL-regblock\n\nThis is probably the most fully featured of the Verilog/SV exporters but it generates\nSV that can't be consumed by all tools. There is a definite verification style to the\nRTL with the use of unpacked structs, interfaces, automatic variables etc.\n\nAdditionally, the code base is so complex that it took less time to implement an exporter\nfrom scratch than to try and fix the issues.\n\nIf you need support for the majority of the SystemRDL features and have commercial EDA\ntools then I'd suggest looking at this package.\n\n### PeakRDL-verilog\n\nThere are two GitHub repos that use this name. The original author has mostly abandonned\ntheir own work in favour of `PeakRDL-regblock` while his work was forked and continues (?)\nto be maintained here: https://github.com/bat52/PeakRDL-verilog\n\nBoth have simple to fix bugs relating to recent versions of Python but the latter project\nhas not enabled issues so further investigation was ruled out.\n\n### OpenTitan RegTool\n\nPerhaps the nicest and cleanest register tool out there is `RegTool`. This is part of the \nopen source OpenTitan project and you can find the documentation here: \nhttps://opentitan.org/book/util/reggen/index.html\n\nThe tool uses its own HJSON schema to define the registers and is somewhat simpler than\nSystemRDL. However, as it has matured, the tooling has become more and more deeply\nembedded in the OT workflows with requirements for metadata driven from the IP blocks\nthat use it. Extracting a generic version of this tool would be a major undertaking and\nimporting the Python tooling into your own project isn't clean.\n\nOn the plus side, the RTL generated is very clean with a module hierarchy that simplifies\nthe work needed on the Python side.\n\n## Implementation Details\n\nThe implementation choices were made to simplify the complexity of the Python RDL\nexporter. Rather than generating a flat RTL view of the whole register file, as is\ndone by many of the current SystemRDL exporters, each field is instantiated as a \nparameterisable Verilog module. This vastly reduces the complexity of both the \ntemplating and the exporter code by moving specialisation into the RTL via generate\nstatements.\n\nThis also happened to be the approach taken by `RegTool` which meant that much of the RTL\ninfrastructure could be taken and modified without much overhead. There is a very clear\nlineage from the OpenTitan work in this exporter in both the RTL and Mako templating.\n\n### RTL Hierarchy\n\nREVISIT: flesh out this section.\n\nThe hierarchy of the generated RTL is shown below:\n\n +---- <block>_reg_pkg\n |\n +---- <block>_reg_top\n |\n +---- rdl_subreg u_field_name_0\n | |\n | +---- rdl_subreg_arg u_arb\n | |\n | +---- rdl_subreg_flop u_flop\n |\n +---- rdl_subreg u_field_name_1\n | |\n | +---- rdl_subreg_arg u_arb\n | |\n | +---- rdl_subreg_flop u_flop\n |\n +---- rdl_subreg u_field_name_2\n |\n ...\n\n\n\n## Installation\n\n```\n$ pip install git+https://github.com/nuquantum/peakrdl-sv\n```\n\n## Usage\n\nThe exporter integrates with PeakRDL via the plugin flow defined here: \nhttps://peakrdl.readthedocs.io/en/latest/for-devs/exporter-plugin.html\n\n```\n$ peakrdl sv -o ./generated <filename.rdl>\n```\n\nYou can also run a standalone script that offers both `export` and `install`\ntargets. The latter will install the required RTL dependencies to a local directory.\nThis can also be done at the `export` stage by passing the `--include-subreg` argument.\n\n```\n$ sv-exporter -h\nusage: sv-exporter [-h] [-v] [-o OUTPUT] {export,install} ...\n\npositional arguments:\n {export,install}\n export Run the SystemVerlog RDL exporter\n install Install SV source files into local tree\n\noptions:\n -h, --help show this help message and exit\n -v, --verbose Enable verbose logging\n -o OUTPUT, --output OUTPUT\n Specify the output path\n\n$ sv-exporter -o ./rtl install\n$ sv-exporter -0 ./rtl export <filename>.rdl\n$ sv-exporter -0 ./rtl export --include-subreg <filename>.rdl\n```\n\n## Limitations\n\nThe following is a list of current limitations and assumptions:\n\n* there is a single toplevel address map\n* only support for a single sw access width\n* no support for register widths > access width\n* no support for countrs\n* no support for aliases\n* no support for interrupt registers\n* no support for halt registers\n* no support for swacc\n* no support for onread side effects\n",
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