# PeakRDL_VIZ
This PeakRDL plugin exports VIZ code for visualizing SystemRDL files contents on MakerChip's online platform.
## Installing
```python3 -m pip install peakrdl-viz```
## How to use
for a quick test for the plugin:
```peakrdl viz -o output_files test_files/long_test.rdl --sv-module [path_to_generated_sv_module]```
import the output .tlv file (inside output_files) to makerchip and test
## Documentation
For more info, read the [documentation](https://peakrdl-viz.readthedocs.io/en/latest/)
Raw data
{
"_id": null,
"home_page": null,
"name": "peakrdl-viz",
"maintainer": null,
"docs_url": null,
"requires_python": ">=3.9",
"maintainer_email": null,
"keywords": "SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, MakerChip, visualization, VIZ, Verilog, SystemVerilog, TL-Verilog, FPGA, ASIC",
"author": "Ali Mohsen",
"author_email": null,
"download_url": "https://files.pythonhosted.org/packages/6c/51/51271de1ecffc36b13ccf556751bdc69b3095eeae99bf0742a128bb16e47/peakrdl_viz-1.0.1.tar.gz",
"platform": null,
"description": "# PeakRDL_VIZ\r\n\r\nThis PeakRDL plugin exports VIZ code for visualizing SystemRDL files contents on MakerChip's online platform.\r\n\r\n## Installing\r\n\r\n```python3 -m pip install peakrdl-viz```\r\n\r\n## How to use\r\n\r\nfor a quick test for the plugin:\r\n\r\n```peakrdl viz -o output_files test_files/long_test.rdl --sv-module [path_to_generated_sv_module]```\r\n\r\nimport the output .tlv file (inside output_files) to makerchip and test\r\n\r\n## Documentation\r\n\r\nFor more info, read the [documentation](https://peakrdl-viz.readthedocs.io/en/latest/)\r\n",
"bugtrack_url": null,
"license": "LGPLv3",
"summary": "Generate visualization code for MakerChip VIZ framework.",
"version": "1.0.1",
"project_urls": {
"Changelog": "https://github.com/balbal1/PeakRDL_Visualization_Plugin/releases",
"Source": "https://github.com/balbal1/PeakRDL_Visualization_Plugin",
"Tracker": "https://github.com/balbal1/PeakRDL_Visualization_Plugin/issues"
},
"split_keywords": [
"systemrdl",
" peakrdl",
" csr",
" compiler",
" tool",
" registers",
" generator",
" makerchip",
" visualization",
" viz",
" verilog",
" systemverilog",
" tl-verilog",
" fpga",
" asic"
],
"urls": [
{
"comment_text": null,
"digests": {
"blake2b_256": "c57b3415e4a46f86211b2559b692e05d13cb135d0efdea7cdfa1db8071ac910c",
"md5": "5d8db0af4a97f357383a01a70c16b948",
"sha256": "dc9af84553ff82cac0e3325f335b0764dd88cb0e502f2c1cfa75ccaf09345d5b"
},
"downloads": -1,
"filename": "peakrdl_viz-1.0.1-py3-none-any.whl",
"has_sig": false,
"md5_digest": "5d8db0af4a97f357383a01a70c16b948",
"packagetype": "bdist_wheel",
"python_version": "py3",
"requires_python": ">=3.9",
"size": 10717,
"upload_time": "2025-07-16T13:35:37",
"upload_time_iso_8601": "2025-07-16T13:35:37.713701Z",
"url": "https://files.pythonhosted.org/packages/c5/7b/3415e4a46f86211b2559b692e05d13cb135d0efdea7cdfa1db8071ac910c/peakrdl_viz-1.0.1-py3-none-any.whl",
"yanked": false,
"yanked_reason": null
},
{
"comment_text": null,
"digests": {
"blake2b_256": "6c5151271de1ecffc36b13ccf556751bdc69b3095eeae99bf0742a128bb16e47",
"md5": "7d9695421ae16d779e438b03a9e06083",
"sha256": "ab85c528a5fafac9482d3959e3a393b383a7e1fa1cce517368aeb922200e5ccc"
},
"downloads": -1,
"filename": "peakrdl_viz-1.0.1.tar.gz",
"has_sig": false,
"md5_digest": "7d9695421ae16d779e438b03a9e06083",
"packagetype": "sdist",
"python_version": "source",
"requires_python": ">=3.9",
"size": 12089,
"upload_time": "2025-07-16T13:35:38",
"upload_time_iso_8601": "2025-07-16T13:35:38.969112Z",
"url": "https://files.pythonhosted.org/packages/6c/51/51271de1ecffc36b13ccf556751bdc69b3095eeae99bf0742a128bb16e47/peakrdl_viz-1.0.1.tar.gz",
"yanked": false,
"yanked_reason": null
}
],
"upload_time": "2025-07-16 13:35:38",
"github": true,
"gitlab": false,
"bitbucket": false,
"codeberg": false,
"github_user": "balbal1",
"github_project": "PeakRDL_Visualization_Plugin",
"travis_ci": false,
"coveralls": false,
"github_actions": true,
"lcname": "peakrdl-viz"
}