# PeakRDL_VIZ
This PeakRDL plugin exports VIZ code for visualizing SystemRDL files contents on MakerChip's online platform.
## Installing
```python3 -m pip install peakrdl-viz```
## How to use
for a quick test for the plugin:
```peakrdl viz -o output_files test_files/long_test.rdl --sv-module [path_to_generated_sv_module]```
import the output .tlv file (inside output_files) to makerchip and test
## Documentation
For more info, read the [documentation](https://peakrdl-viz.readthedocs.io/en/latest/)
Raw data
{
"_id": null,
"home_page": null,
"name": "peakrdl-viz",
"maintainer": null,
"docs_url": null,
"requires_python": ">=3.9",
"maintainer_email": null,
"keywords": "SystemRDL, PeakRDL, CSR, compiler, tool, registers, generator, MakerChip, visualization, VIZ, Verilog, SystemVerilog, TL-Verilog, FPGA, ASIC",
"author": "Ali Mohsen",
"author_email": null,
"download_url": "https://files.pythonhosted.org/packages/ad/ca/cc300cc2a4d57c9ed061619b18cd8f7f2477311c50b199233de353bce80f/peakrdl_viz-1.0.2.tar.gz",
"platform": null,
"description": "# PeakRDL_VIZ\n\nThis PeakRDL plugin exports VIZ code for visualizing SystemRDL files contents on MakerChip's online platform.\n\n## Installing\n\n```python3 -m pip install peakrdl-viz```\n\n## How to use\n\nfor a quick test for the plugin:\n\n```peakrdl viz -o output_files test_files/long_test.rdl --sv-module [path_to_generated_sv_module]```\n\nimport the output .tlv file (inside output_files) to makerchip and test\n\n## Documentation\n\nFor more info, read the [documentation](https://peakrdl-viz.readthedocs.io/en/latest/)\n",
"bugtrack_url": null,
"license": "LGPLv3",
"summary": "Generate visualization code for MakerChip VIZ framework.",
"version": "1.0.2",
"project_urls": {
"Changelog": "https://github.com/balbal1/PeakRDL_Visualization_Plugin/releases",
"Source": "https://github.com/balbal1/PeakRDL_Visualization_Plugin",
"Tracker": "https://github.com/balbal1/PeakRDL_Visualization_Plugin/issues"
},
"split_keywords": [
"systemrdl",
" peakrdl",
" csr",
" compiler",
" tool",
" registers",
" generator",
" makerchip",
" visualization",
" viz",
" verilog",
" systemverilog",
" tl-verilog",
" fpga",
" asic"
],
"urls": [
{
"comment_text": null,
"digests": {
"blake2b_256": "a93ae2c546e6e68ad7bcbd1ad1da77de7979bac7f85ee516c0aaf6e4cc6dc461",
"md5": "4ab2df4674ed3032a6db20d22060468a",
"sha256": "ff2e7107a7c352c8af370ffa4af62954cca9cc0413fb3f902a22d318b6633039"
},
"downloads": -1,
"filename": "peakrdl_viz-1.0.2-py3-none-any.whl",
"has_sig": false,
"md5_digest": "4ab2df4674ed3032a6db20d22060468a",
"packagetype": "bdist_wheel",
"python_version": "py3",
"requires_python": ">=3.9",
"size": 12820,
"upload_time": "2025-08-13T18:29:37",
"upload_time_iso_8601": "2025-08-13T18:29:37.904354Z",
"url": "https://files.pythonhosted.org/packages/a9/3a/e2c546e6e68ad7bcbd1ad1da77de7979bac7f85ee516c0aaf6e4cc6dc461/peakrdl_viz-1.0.2-py3-none-any.whl",
"yanked": false,
"yanked_reason": null
},
{
"comment_text": null,
"digests": {
"blake2b_256": "adcacc300cc2a4d57c9ed061619b18cd8f7f2477311c50b199233de353bce80f",
"md5": "c44f87e1ee5fe9e3e0440052970856ee",
"sha256": "5a6609de6876ba469cb12c9ce28c376094dfa052a1e6e1e920be955373b5e7d2"
},
"downloads": -1,
"filename": "peakrdl_viz-1.0.2.tar.gz",
"has_sig": false,
"md5_digest": "c44f87e1ee5fe9e3e0440052970856ee",
"packagetype": "sdist",
"python_version": "source",
"requires_python": ">=3.9",
"size": 135778,
"upload_time": "2025-08-13T18:29:39",
"upload_time_iso_8601": "2025-08-13T18:29:39.374491Z",
"url": "https://files.pythonhosted.org/packages/ad/ca/cc300cc2a4d57c9ed061619b18cd8f7f2477311c50b199233de353bce80f/peakrdl_viz-1.0.2.tar.gz",
"yanked": false,
"yanked_reason": null
}
],
"upload_time": "2025-08-13 18:29:39",
"github": true,
"gitlab": false,
"bitbucket": false,
"codeberg": false,
"github_user": "balbal1",
"github_project": "PeakRDL_Visualization_Plugin",
"travis_ci": false,
"coveralls": false,
"github_actions": true,
"lcname": "peakrdl-viz"
}