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An abstract VHDL language model written in Python.
# Main Goals
This package provides a unified abstract language model for VHDL.
Projects reading from source files can derive own classes and implement additional logic to create a concrete language
model for their tools.
Projects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services
on such a model, while supporting multiple frontends.
# Use Cases
## pyVHDLModel Generators
* High-level API for [GHDL's](https://GitHub.com/ghdl/ghdl) `libghdl` offered via `pyghdl`.
* Code Document-Object-Model (Code-DOM) in [pyVHDLParser](https://GitHub.com/Paebbels/pyVHDLParser).
## pyVHDLModel Consumers
* Create graphical views of VHDL files or designs.
Possible candidates: [Symbolator](https://GitHub.com/kevinpt/symbolator)
* Created a (re)formatted output of VHDL.
# Examples
## List all Entities with Generics and Ports
The following tiny example is based on GHDL's [`pyGHDL.dom`](https://GitHub.com/ghdl/ghdl/tree/master/pyGHDL/dom) package implementing
pyVHDLModel.
```python
from pathlib import Path
from pyGHDL.dom.NonStandard import Design, Document
sourceFile = Path("example.vhdl")
design = Design()
library = design.GetLibrary("lib")
document = Document(sourceFile)
design.AddDocument(document, library)
for entity in document.Entities.values():
print(f"{entity.Identifier}")
print(" generics:")
for generic in entity.GenericItems:
identifiers = ", ".join([str(i) for i in generic.Identifiers])
print(f" - {identifiers} : {generic.Mode!s} {generic.Subtype}")
print(" ports:")
for port in entity.PortItems:
identifiers = ", ".join([str(i) for i in port.Identifiers])
print(f" - {identifiers} : {port.Mode!s} {port.Subtype}")
```
# Contributors
* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)
* [Unai Martinez-Corral](https://GitHub.com/umarcor)
* [and more...](https://GitHub.com/VHDL/pyVHDLModel/graphs/contributors)
# License
This Python package (source code) licensed under [Apache License 2.0](LICENSE.md).
The accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).
-------------------------
SPDX-License-Identifier: Apache-2.0
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"description": "<p align=\"center\">\n <a title=\"vhdl.github.io/pyVHDLModel\" href=\"https://vhdl.github.io/pyVHDLModel\"><img height=\"80px\" src=\"doc/_static/logo.svg\"/></a>\n</p>\n\n[](https://github.com/vhdl/pyVHDLModel)\n[](LICENSE.md)\n[](https://vhdl.github.io/pyVHDLModel/)\n[](LICENSE.md)\n[](https://gitter.im/hdl/community) \n[](https://pypi.org/project/pyVHDLModel/)\n\n \n[](https://github.com/VHDL/pyVHDLModel/actions/workflows/Pipeline.yml)\n[](https://libraries.io/github/vhdl/pyVHDLModel)\n[](https://www.codacy.com/gh/VHDL/pyVHDLModel)\n[](https://www.codacy.com/gh/VHDL/pyVHDLModel)\n[](https://codecov.io/gh/vhdl/pyVHDLModel)\n\n<!--\n[](https://github.com/vhdl/pyVHDLModel/network/dependents)\n[](https://libraries.io/github/vhdl/pyVHDLModel/sourcerank)\n-->\n\nAn abstract VHDL language model written in Python.\n\n\n# Main Goals\n\nThis package provides a unified abstract language model for VHDL.\nProjects reading from source files can derive own classes and implement additional logic to create a concrete language\nmodel for their tools.\n\nProjects consuming pre-processed VHDL data (parsed, analyzed or elaborated) can build higher level features and services\non such a model, while supporting multiple frontends.\n\n\n# Use Cases\n\n## pyVHDLModel Generators\n\n* High-level API for [GHDL's](https://GitHub.com/ghdl/ghdl) `libghdl` offered via `pyghdl`.\n* Code Document-Object-Model (Code-DOM) in [pyVHDLParser](https://GitHub.com/Paebbels/pyVHDLParser).\n\n## pyVHDLModel Consumers\n\n* Create graphical views of VHDL files or designs. \n\tPossible candidates: [Symbolator](https://GitHub.com/kevinpt/symbolator)\n* Created a (re)formatted output of VHDL.\n\n\n# Examples\n\n## List all Entities with Generics and Ports\n\nThe following tiny example is based on GHDL's [`pyGHDL.dom`](https://GitHub.com/ghdl/ghdl/tree/master/pyGHDL/dom) package implementing\npyVHDLModel.\n\n```python\nfrom pathlib import Path\nfrom pyGHDL.dom.NonStandard import Design, Document\n\nsourceFile = Path(\"example.vhdl\")\n\ndesign = Design()\nlibrary = design.GetLibrary(\"lib\")\ndocument = Document(sourceFile)\ndesign.AddDocument(document, library)\n\nfor entity in document.Entities.values():\n print(f\"{entity.Identifier}\")\n print(\" generics:\")\n for generic in entity.GenericItems:\n identifiers = \", \".join([str(i) for i in generic.Identifiers])\n print(f\" - {identifiers} : {generic.Mode!s} {generic.Subtype}\")\n print(\" ports:\")\n for port in entity.PortItems:\n identifiers = \", \".join([str(i) for i in port.Identifiers])\n print(f\" - {identifiers} : {port.Mode!s} {port.Subtype}\")\n```\n\n\n# Contributors\n\n* [Patrick Lehmann](https://GitHub.com/Paebbels) (Maintainer)\n* [Unai Martinez-Corral](https://GitHub.com/umarcor)\n* [and more...](https://GitHub.com/VHDL/pyVHDLModel/graphs/contributors)\n\n\n# License\n\nThis Python package (source code) licensed under [Apache License 2.0](LICENSE.md). \nThe accompanying documentation is licensed under [Creative Commons - Attribution 4.0 (CC-BY 4.0)](doc/Doc-License.rst).\n\n-------------------------\nSPDX-License-Identifier: Apache-2.0\n",
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