PyDigger - unearthing stuff about Python


NameVersionSummarydate
slvcodec 0.4.17 Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. 2021-07-21 22:43:34
crcgen 2.1 CRC algorithm code generator 2021-07-17 13:35:12
pyVHDLModel 0.11.2 An abstract VHDL language model. 2021-07-16 07:33:41
dovado-rtl 0.7.12 CLI tool for RTL Design Space Exploration on top of Vivado 2021-07-12 10:44:13
hdlConvertor 2.3 VHDL and System Verilog parser written in c++ 2021-07-02 13:33:32
sphinx-hwt 2.7 Sphinx extension to produce interactive schematic for hardware written in HWT 2021-07-02 06:20:08
hdlConvertorAst 1.0 A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities 2021-07-01 20:31:55
hectare 0.2.4 VHDL generator from SystemRDL 2021-06-20 15:59:34
pyVHDLParser 0.6.3 A streaming-based VHDL parser. 2021-06-10 10:06:20
vsg 3.2.2 VHDL Style Guide 2021-06-09 19:37:55
thdl 0.0.6 thdl 2021-05-18 12:59:44
ipxact2systemverilog 1.0.12 Generate VHDL, SystemVerilog, html, rst, md, pdf from an IPXACT description 2021-05-17 16:40:12
edalize 0.2.5 Edalize is a library for interfacing EDA tools, primarily for FPGA development 2021-05-12 14:40:06
hdl-checker 0.7.3 HDL code checker 2021-04-12 08:16:10
fusesoc 1.12.0 FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code. 2021-02-25 21:38:30
fsva 0.0.8 fsva (FuseSoc Verification Automation) 2021-01-21 15:43:48
axilent 0.1.8 Tools for describing a sequence of Axi4Lite commands. 2021-01-14 17:43:30
xeda 0.0.1.post1.dev0 XEDA: Cross-platform, cross-tool, cross-target, cross-HDL Electronic Design Automation 2020-09-04 18:12:16
vhdre 0.2 VHDL code generator for matching regular expressions. 2019-05-16 10:05:09
uart 0.5.4 Utility for simply creating and modifying VHDL bus slave modules 2018-04-03 11:44:54
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