| Name | Version | Summary | date |
| fsva |
0.0.7 |
fsva (FuseSoc Verification Automation) |
2021-01-15 12:02:44 |
| axilent |
0.1.8 |
Tools for describing a sequence of Axi4Lite commands. |
2021-01-14 17:43:30 |
| slvcodec |
0.4.10 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2021-01-14 17:39:17 |
| dovado-rtl |
0.4.2 |
CLI tool for RTL Design Space Exploration on top of Vivado |
2021-01-06 20:38:12 |
| pyVHDLModel |
0.8.0 |
An abstract VHDL language model. |
2021-01-03 23:12:33 |
| pyVHDLParser |
0.6.0 |
A streaming-based VHDL parser. |
2020-12-01 00:09:43 |
| edalize |
0.2.3 |
Edalize is a library for interfacing EDA tools, primarily for FPGA development |
2020-11-17 22:05:37 |
| hdl-checker |
0.7.2 |
HDL code checker |
2020-11-14 19:35:25 |
| hdlConvertorAst |
0.6 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2020-11-01 23:19:34 |
| vsg |
2.2.0 |
VHDL Style Guide |
2020-10-08 22:35:04 |
| sphinx-hwt |
2.6 |
Sphinx extension to produce interactive schematic for hardware written in HWT |
2020-10-03 09:29:20 |
| hdlConvertor |
2.1 |
VHDL and System Verilog parser written in c++ |
2020-09-06 20:54:36 |
| xeda |
0.0.1.post1.dev0 |
XEDA: Cross-platform, cross-tool, cross-target, cross-HDL Electronic Design Automation |
2020-09-04 18:12:16 |
| fusesoc |
1.11.0 |
FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code. |
2020-06-16 14:38:49 |
| hectare |
0.2.0 |
VHDL generator from SystemRDL |
2020-06-08 06:56:27 |
| vhdre |
0.2 |
VHDL code generator for matching regular expressions. |
2019-05-16 10:05:09 |
| uart |
0.5.4 |
Utility for simply creating and modifying VHDL bus slave modules |
2018-04-03 11:44:54 |
| pywire |
1.0.0 |
A library for generating VHDL, designed for use in FPGAs |
2018-02-11 20:26:10 |
| polyphony |
0.3.3 |
Python based High Level Synthesis compiler |
2017-12-26 02:31:01 |
| ipxact2systemverilog |
1.0.4 |
Generate VHDL, SystemVerilog, html, rst, pdf from an IPXACT description |
2017-12-18 21:31:06 |