PyDigger - unearthing stuff about Python


NameVersionSummarydate
vsc-dm 0.0.1.14676776726 Core Verification Stimulus and Coverage library 2025-04-26 02:31:00
vsc-solvers 0.0.1.13937968163 Core Verification Stimulus and Coverage library 2025-03-19 03:09:55
pyhdl-if 0.0.2.13849311719 Python interface for HDL programming interfaces 2025-03-14 03:34:25
zuspec-sv 0.0.9 Core ARL data model library 2025-02-12 03:02:40
zuspec-be-sw 0.0.9 Backend library to generate software output 2025-02-12 02:45:03
zuspec-arl-eval 0.0.9 Core ARL data model library 2025-02-12 02:44:37
zuspec-arl-dm 0.0.9 Core ARL data model library 2025-02-12 02:37:06
ivpm 1.1.4.13232874283 IVPM (IP and Verification Package Manager) is a project-internal package manager. 2025-02-10 03:20:24
pytest-fv 0.0.1.13065020602 pytest extensions to support running functional-verification jobs 2025-01-31 02:09:45
zuspec-dataclasses 0.0.1.13064594382 Front-end for capturing Action Relation Level models using dataclasses 2025-01-31 01:29:39
pyvsc-dataclasses 0.0.1.12773179088 Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses 2025-01-14 17:33:41
mooreio-client 2.0.4 CLI tool to automate EDA tasks for ASICs, FPGAs, and UVM IP. 2024-11-28 20:18:13
pySVModel 0.5.1 An abstract SystemVerilog language model (incl. Verilog). 2024-11-11 23:50:21
svdata 0.0.16 Parse systemverilog files in Python. 2024-10-29 10:33:53
cocotb-vivado 0.0.4 Limited cocotb/Python interface for Xilinx Vivado Simulator 2024-10-01 09:56:57
pyucis 0.1.4.11087239919 PyUCIS provides a Python API for manipulating UCIS coverage data. 2024-09-28 21:47:24
sv-simpleparser 0.0.7 A simple SystemVerilog parser 2024-08-26 16:27:12
mio-cli 1.3.8 The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. 2024-05-17 12:13:59
pyhdl-call-if 0.0.1.8682446142 Python interface for HDL programming interfaces 2024-04-15 02:48:41
pyhdl-tlm-if 0.0.1 Python interface for HDL programming interfaces 2024-04-13 19:18:52
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