| Name | Version | Summary | date |
| ivpm |
1.1.3.10755799818 |
IVPM (IP and Verification Package Manager) is a project-internal package manager. |
2024-09-08 01:03:44 |
| pytest-fv |
0.0.1.10755651477 |
pytest extensions to support running functional-verification jobs |
2024-09-08 00:41:14 |
| zuspec-sv |
0.0.1.10730567428 |
Core ARL data model library |
2024-09-06 01:13:18 |
| pyapi-compat-if |
0.0.1.10710515114 |
Core Verification Stimulus and Coverage library |
2024-09-04 22:33:20 |
| zuspec-arl-eval |
0.0.1.10707232152 |
Core ARL data model library |
2024-09-04 18:19:39 |
| vsc-solvers |
0.0.1.10703256703 |
Core Verification Stimulus and Coverage library |
2024-09-04 14:06:07 |
| vsc-dm |
0.0.1.10703122859 |
Core Verification Stimulus and Coverage library |
2024-09-04 13:56:00 |
| zuspec-arl-dm |
0.0.1.10635791863 |
Core ARL data model library |
2024-08-30 16:13:05 |
| sv-simpleparser |
0.0.7 |
A simple SystemVerilog parser |
2024-08-26 16:27:12 |
| pyhdl-if |
0.0.1.10542878700 |
Python interface for HDL programming interfaces |
2024-08-25 01:03:43 |
| svdata |
0.0.15 |
Parse systemverilog files in Python. |
2024-08-01 12:51:49 |
| zuspec-be-sw |
0.0.1.9831947446 |
Backend library to generate software output |
2024-07-08 01:21:16 |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| pyhdl-call-if |
0.0.1.8682446142 |
Python interface for HDL programming interfaces |
2024-04-15 02:48:41 |
| pyhdl-tlm-if |
0.0.1 |
Python interface for HDL programming interfaces |
2024-04-13 19:18:52 |
| pyhdl-pi-if |
0.0.1.8675558542 |
Python interface for HDL programming interfaces |
2024-04-13 18:44:50 |
| pyvsc-dataclasses |
0.0.1.8548344824 |
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses |
2024-04-04 02:20:33 |
| ipxact2sv |
1.0.6 |
Generate SystemVerilog, html, rst, md, pdf, docx, C headers from an IPXACT description |
2024-03-11 19:56:34 |
| peakrdl-sv |
0.0.1 |
A SystemRDL exporter for SystemVerilog |
2024-03-07 11:54:22 |
| magia-hdl |
0.5.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-02-20 20:35:45 |