| Name | Version | Summary | date |
| pyhdl-tlm-if |
0.0.1 |
Python interface for HDL programming interfaces |
2024-04-13 19:18:52 |
| pyhdl-pi-if |
0.0.1.8675558542 |
Python interface for HDL programming interfaces |
2024-04-13 18:44:50 |
| ipxact2sv |
1.0.6 |
Generate SystemVerilog, html, rst, md, pdf, docx, C headers from an IPXACT description |
2024-03-11 19:56:34 |
| peakrdl-sv |
0.0.1 |
A SystemRDL exporter for SystemVerilog |
2024-03-07 11:54:22 |
| magia-hdl |
0.5.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-02-20 20:35:45 |
| magia-ip |
0.0.1 |
IP libraries designed with Magia |
2024-02-18 21:21:15 |
| syn-magia |
0.3.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-01-06 20:57:03 |
| sverilogpy |
0.0.0a2 |
A python System Verilog Parser and AST |
2024-01-03 16:47:25 |
| hdlConvertorAst |
1.2 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2023-10-23 13:53:41 |
| ipsocgen |
0.1.39 |
Generic SoC builder in HDL |
2023-06-24 22:45:09 |
| libarl |
0.0.1.3625797450 |
Core ARL model evaluator library |
2022-12-06 02:24:00 |
| libvsc |
0.0.1.3615208868 |
Core Verification Stimulus and Coverage library |
2022-12-04 21:50:55 |