# IP SoC Generator
**IP SoC gen** is a framework to generate MP/SoCs with different configurations through a set of masters/slaves for fast
digital design development. To install through pip:
```bash
pip install --upgrade ipsocgen
```
## Template projects
In order to get started generating your own designs, check the [template
repository](https://github.com/aignacio/ipsocgen_template) which contains an example of SoC and MPSoC using
[NoX](https://github.com/aignacio/nox)
processor as the main CPU. The configuration files that were used for the **ipsocgen_template** are available in [`ipsocgen/examples/template_soc.yaml`](ipsocgen/examples/template_soc.yaml) and [`ipsocgen/examples/template_mpsoc.yaml`](ipsocgen/examples/template_mpsoc.yaml).
## To contribute/develop/extend the work
Please follow the steps below to build the virtual environment and install the dependencies.
```bash
python3 -m venv venv
source venv/bin/activate
python3 setup.py install
```
## Configuration file reference
Here is a list of all inputs that can be listed for the IPSoCGen configuration file in yaml format.
```yaml
proj_name: #Project Name
desc: #Short description
type: #System type (soc or mpsoc)
#####################
# If type == soc
#####################
soc_desc:
bus_name: #Name for the bus Interconnect
bus_type: #Type of the bus
addr_width: #Bus adress width
data_width: #Bus data width
txn_id_width: #Bus transaction ID width
num_masters: #Number of master in the bus (min == 1)
num_slaves: #Number of slave in the bus (min == 1)
proc_required: #Set if a processor is required (y or n)
mmap_type: #Memory map type (manual or auto)
clk:
name: #Clock name
clk_int: #Internal signal name for the clock
io_in_clk: #Wrapper input pin for the clock
type: #Type of clock (pll or direct)
pll: #Only applicable if type == pll
divclk_divide: #PLL parameters
clkfbout_mult: #PLL parameters
clkout_divide: #PLL parameters
io_rst_pin: #Wrapper input pin for the PLL reset
rst_in_type: #Type of reset for the PLL (act_l or act_h)
clkin_period: #PLL parameters
rst:
name: #Reset name
rst_int: #Internal signal name for the reset
io_in_rst: #Wrapper input pin for the reset
rst_in_type: #Type of reset for the PLL (act_l or act_h)
type: #Type of reset (acc_rst or direct)
proc:
name: #Name of the main CPU that will be used
type: #Type of processor (nox, vex…)
clk: #Describe the clock of the processor
rst: #Describe the reset of the processor
boot: #Describe the boot for this processor
type: #Type of boot (slave, value or signal)
signal: #Only applicable if type == signal
slave: #Only applicable if type == slave
value: #Only applicable if type == value
irq_mapping:
timer: #Internal signal name for RV timer interrupts
software: #Internal signal name for RV software interrupts
external: #Internal signal name for RV external interrupts
masters: #Describe all masters within the system
x: #Master ID, start always from 0
name: #Unique name for the instance
desc: #Brief description of the master I/F
type: #Master type
if: #Interface name (must be a valid one supported)
...
slaves:
x: #Slave ID, start always from 0
name: #Unique name for the instance
desc: #Brief description of the slave
type: #Slave type
base_addr: #Base address if mmap_type == manual
addr_width: #Base address if mmap_type == manual
mem_size_kib: #Slave kib size, only applicable if type == ram_mem/rom_mem/acc_custom_slave
irq_timer: #Timer internal signal name, only applicable if type == acc_timer
rst_def_addr: #Reset default address, only applicable if type == acc_rst
rst_addr_out: #Reset address signal name [usually for CPUs], only applicable if type == acc_rst
rst_pulse_width: #Reset address signal name [usually for CPUs], only applicable if type == acc_rst
io_bootloader: #Wrapper input pin for the bootloader, only applicable if type == acc_rst
bootloader_type: #Bootloader type (act_l or act_h), only applicable if type == acc_rst
irq_dma_done: #Internal signal name for the DMA done IRQ, only applicable if type == acc_dma
irq_dma_error: #Internal signal name for the DMA error IRQ, only applicable if type == acc_dma
io_tx: #Wrapper output pin for the UART TX, only applicable if type == acc_uart
io_rx: #Wrapper input pin for the UART TX, only applicable if type == acc_uart
irq_uart_rx: #Internal signal name for the UART IRQ, only applicable if type == acc_uart
irq_type: #IRQ type (0-level, 1-edge) for all incomming IRQs, only applicable if type == acc_irq
irq_summary: #Internal signal name for the IRQ summary, only applicable if type == acc_irq
vec_mapping: #List of all internal signal names for the IRQ vector, only applicable if type == acc_irq
- highest_prior_irq_1
- …
- lowest_prior_irq_n
irq_noc: #Internal signal name for the NoC IRQ, only applicable if type == acc_noc
pkt_recv_irq: #Internal signal name for the Received Packet IRQ, only applicable if type == acc_eth
pkt_sent_irq: #Internal signal name for the Packet sent IRQ, only applicable if type == acc_eth
pkt_recv_full_irq: #Internal signal name for the Full FIFO Recv. Packet IRQ, only applicable if type == acc_eth
eth_type: #Ethernet slave type (csr, infifo or outfifo), only applicable if type == acc_eth
...
#####################
# If type == mpsoc
#####################
mpsoc_desc:
clk:
name: #Clock name
clk_int: #Internal signal name for the clock
io_in_clk: #Wrapper input pin for the clock
type: #Type of clock (pll or direct)
pll: #Only applicable if type == pll
divclk_divide: #PLL parameters
clkfbout_mult: #PLL parameters
clkout_divide: #PLL parameters
io_rst_pin: #Wrapper input pin for the PLL reset
rst_in_type: #Type of reset for the PLL (act_l or act_h)
clkin_period: #PLL parameters
rst:
name: #Reset name
rst_int: #Internal signal name for the reset
io_in_rst: #Wrapper input pin for the reset
rst_in_type: #Type of reset for the PLL (act_l or act_h)
type: #Type of reset (acc_rst or direct)
noc:
type: #Type of the noc (currently only ravenoc is available)
name: #Unique name for the NoC instance
size_x: #Num. of rows
size_y: #Num. of collumns
flit_data_width: #Data width of the flit
flit_buff: #Num. of flit buffers
h_priority: #Priority of the virtual channels (ZeroHighPrior or ZeroLowPrior)
n_virt_chn: #Num. of virtual channels
routing_alg: #Routing algorithm (XYAlg or YXAlg)
max_sz_pkt: #Max. size of packet in flits (usually 256)
base_addr: #NoC common base address across all Tiles
tiles:
x: #Tile ID, always start from zero
.... #Same description pattern as soc_desc
```
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"description": "\n# IP SoC Generator\n\n**IP SoC gen** is a framework to generate MP/SoCs with different configurations through a set of masters/slaves for fast\ndigital design development. To install through pip: \n```bash\npip install --upgrade ipsocgen\n```\n\n## Template projects \nIn order to get started generating your own designs, check the [template\nrepository](https://github.com/aignacio/ipsocgen_template) which contains an example of SoC and MPSoC using\n[NoX](https://github.com/aignacio/nox)\nprocessor as the main CPU. The configuration files that were used for the **ipsocgen_template** are available in [`ipsocgen/examples/template_soc.yaml`](ipsocgen/examples/template_soc.yaml) and [`ipsocgen/examples/template_mpsoc.yaml`](ipsocgen/examples/template_mpsoc.yaml).\n\n## To contribute/develop/extend the work\nPlease follow the steps below to build the virtual environment and install the dependencies.\n```bash\npython3 -m venv venv\nsource venv/bin/activate \npython3 setup.py install\n```\n## Configuration file reference\n\nHere is a list of all inputs that can be listed for the IPSoCGen configuration file in yaml format.\n```yaml\nproj_name: #Project Name\ndesc: \t #Short description\ntype: #System type (soc or mpsoc)\n\n#####################\n# If type == soc\n#####################\n\nsoc_desc:\n bus_name:\t\t #Name for the bus Interconnect\n bus_type:\t \t #Type of the bus\n addr_width: \t #Bus adress width\t\t\t\n data_width:\t \t #Bus data width\n txn_id_width: \t #Bus transaction ID width\n num_masters:\t #Number of master in the bus (min == 1)\n num_slaves: \t #Number of slave in the bus (min == 1)\n proc_required:\t #Set if a processor is required (y or n)\n mmap_type: \t #Memory map type (manual or auto)\n clk:\n name: \t\t #Clock name\n clk_int: \t\t #Internal signal name for the clock\n io_in_clk: \t\t #Wrapper input pin for the clock\n type: \t\t #Type of clock (pll or direct)\n pll: \t\t #Only applicable if type == pll\n divclk_divide: #PLL parameters\n clkfbout_mult:\t #PLL parameters\n clkout_divide:\t #PLL parameters\n io_rst_pin: #Wrapper input pin for the PLL reset\n rst_in_type: #Type of reset for the PLL (act_l or act_h)\n clkin_period: #PLL parameters\n rst: \n name: \t\t #Reset name\n rst_int: \t\t #Internal signal name for the reset\n io_in_rst: \t\t #Wrapper input pin for the reset\n rst_in_type: \t #Type of reset for the PLL (act_l or act_h)\n type: \t\t #Type of reset (acc_rst or direct)\n proc:\t\t\n name: \t\t #Name of the main CPU that will be used\n type:\t\t #Type of processor (nox, vex\u2026)\n clk: \t\t #Describe the clock of the processor\n rst: \t\t #Describe the reset of the processor\n boot:\t\t #Describe the boot for this processor\n type: \t \t #Type of boot (slave, value or signal)\n signal: \t \t #Only applicable if type == signal\n slave: \t\t #Only applicable if type == slave\n value: \t #Only applicable if type == value\n irq_mapping:\n timer: \t\t #Internal signal name for RV timer interrupts\n software: \t\t #Internal signal name for RV software interrupts\n external: \t\t #Internal signal name for RV external interrupts\n masters:\t\t #Describe all masters within the system\n x:\t\t #Master ID, start always from 0\n name: \t\t #Unique name for the instance\n desc: \t\t #Brief description of the master I/F\n type: \t \t #Master type\n if: \t\t #Interface name (must be a valid one supported)\n ...\n slaves:\n x:\t\t #Slave ID, start always from 0\n name: \t\t #Unique name for the instance\n desc: \t\t #Brief description of the slave\n type:\t\t #Slave type\n base_addr:\t #Base address if mmap_type == manual\n addr_width:\t #Base address if mmap_type == manual\n mem_size_kib:\t #Slave kib size, only applicable if type == ram_mem/rom_mem/acc_custom_slave\n irq_timer:\t\t #Timer internal signal name, only applicable if type == acc_timer\n rst_def_addr:\t #Reset default address, only applicable if type == acc_rst\n rst_addr_out:\t #Reset address signal name [usually for CPUs], only applicable if type == acc_rst\n rst_pulse_width: \t #Reset address signal name [usually for CPUs], only applicable if type == acc_rst\n io_bootloader:\t #Wrapper input pin for the bootloader, only applicable if type == acc_rst\n bootloader_type: #Bootloader type (act_l or act_h), only applicable if type == acc_rst\n irq_dma_done:\t #Internal signal name for the DMA done IRQ, only applicable if type == acc_dma\n irq_dma_error: \t #Internal signal name for the DMA error IRQ, only applicable if type == acc_dma\n io_tx:\t\t #Wrapper output pin for the UART TX, only applicable if type == acc_uart\n io_rx:\t\t #Wrapper input pin for the UART TX, only applicable if type == acc_uart\n irq_uart_rx:\t #Internal signal name for the UART IRQ, only applicable if type == acc_uart\n irq_type:\t\t #IRQ type (0-level, 1-edge) for all incomming IRQs, only applicable if type == acc_irq\n irq_summary:\t #Internal signal name for the IRQ summary, only applicable if type == acc_irq\n vec_mapping:\t #List of all internal signal names for the IRQ vector, only applicable if type == acc_irq\n - highest_prior_irq_1\n - \u2026\n - lowest_prior_irq_n\n irq_noc:\t \t #Internal signal name for the NoC IRQ, only applicable if type == acc_noc\n pkt_recv_irq:\t #Internal signal name for the Received Packet IRQ, only applicable if type == acc_eth\n pkt_sent_irq:\t #Internal signal name for the Packet sent IRQ, only applicable if type == acc_eth\n pkt_recv_full_irq:\t#Internal signal name for the Full FIFO Recv. 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