| Name | Version | Summary | date |
| polyphony |
0.4.0 |
Python based High Level Synthesis compiler |
2025-01-29 10:02:37 |
| myhdl |
0.11.51 |
Python as a Hardware Description Language |
2024-12-21 16:28:31 |
| hdl21 |
7.0.0 |
Hardware Description Library |
2024-12-12 17:25:31 |
| sandpiper-saas |
1.1.0 |
Sandpiper SaaS |
2024-08-26 21:51:46 |
| liteiclink |
2023.12 |
Small footprint and configurable Inter-Chip communication cores |
2024-04-18 20:33:04 |
| magia-hdl |
0.5.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-02-20 20:35:45 |
| magia-ip |
0.0.1 |
IP libraries designed with Magia |
2024-02-18 21:21:15 |
| syn-magia |
0.3.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-01-06 20:57:03 |
| hdlConvertor-binary |
2.3 |
VHDL and System Verilog parser written in c++ |
2024-01-06 00:37:35 |
| litex |
2023.12 |
Python SoC/Core builder for building FPGA based systems. |
2023-12-28 20:49:13 |
| hdlConvertorAst |
1.2 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2023-10-23 13:53:41 |
| sphinxcontrib-hdl-diagrams |
0.0.post160 |
Generate diagrams from HDL in Sphinx. |
2023-09-21 05:39:48 |
| litedram |
2023.8 |
Small footprint and configurable DRAM core |
2023-09-17 22:02:31 |
| ipsocgen |
0.1.39 |
Generic SoC builder in HDL |
2023-06-24 22:45:09 |
| liteeth |
2022.12 |
Small footprint and configurable Ethernet core |
2023-04-11 18:09:25 |
| litepcie |
2022.12 |
Small footprint and configurable PCIe core |
2023-04-07 23:10:42 |
| ipyxact |
0.3.2 |
Python IP-Xact handling library |
2022-06-15 20:30:00 |
| migen |
0.9.2 |
Python toolbox for building complex digital hardware |
2019-11-03 18:16:27 |