| Name | Version | Summary | date |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| ivpm |
1.1.2.9116518260 |
IVPM (IP and Verification Package Manager) is a project-internal package manager. |
2024-05-16 17:20:39 |
| pyhdl-if |
0.0.1.9053152306 |
Python interface for HDL programming interfaces |
2024-05-12 17:42:56 |
| pyhdl-call-if |
0.0.1.8682446142 |
Python interface for HDL programming interfaces |
2024-04-15 02:48:41 |
| pyhdl-tlm-if |
0.0.1 |
Python interface for HDL programming interfaces |
2024-04-13 19:18:52 |
| pyhdl-pi-if |
0.0.1.8675558542 |
Python interface for HDL programming interfaces |
2024-04-13 18:44:50 |
| pyvsc-dataclasses |
0.0.1.8548344824 |
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses |
2024-04-04 02:20:33 |
| vsc-solvers |
0.0.1.8469955330 |
Core Verification Stimulus and Coverage library |
2024-03-28 15:51:20 |
| pyapi-compat-if |
0.0.1.8428028712 |
Core Verification Stimulus and Coverage library |
2024-03-25 22:51:34 |
| zuspec-arl-eval |
0.0.1.8427873686 |
Core ARL data model library |
2024-03-25 22:37:52 |
| vsc-dm |
0.0.1.8421861683 |
Core Verification Stimulus and Coverage library |
2024-03-25 14:37:50 |
| zuspec-arl-dm |
0.0.1.8412024765 |
Core ARL data model library |
2024-03-24 20:51:23 |
| zuspec-sv |
0.0.1.8404632036 |
Core ARL data model library |
2024-03-23 21:42:55 |
| ipxact2sv |
1.0.6 |
Generate SystemVerilog, html, rst, md, pdf, docx, C headers from an IPXACT description |
2024-03-11 19:56:34 |
| peakrdl-sv |
0.0.1 |
A SystemRDL exporter for SystemVerilog |
2024-03-07 11:54:22 |
| magia-hdl |
0.5.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-02-20 20:35:45 |
| magia-ip |
0.0.1 |
IP libraries designed with Magia |
2024-02-18 21:21:15 |
| rtlpy |
1.0.3 |
A Library of Python Utilities for RTL Design |
2024-02-15 18:19:25 |
| cocotb-vivado |
0.0.3 |
Limited cocotb/Python interface for Xilinx Vivado Simulator |
2024-02-12 10:28:27 |
| syn-magia |
0.3.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-01-06 20:57:03 |