Name | Version | Summary | date |
tsfpga |
12.3.6 |
A flexible and scalable development platform for modern FPGA projects |
2024-08-27 13:35:28 |
enerbitdso |
0.1.11 |
enerBit DSO (Distribution System Operator) API client |
2024-07-24 15:40:38 |
myhdl |
0.11.49 |
Python as a Hardware Description Language |
2024-06-14 06:42:15 |
liteiclink |
2023.12 |
Small footprint and configurable Inter-Chip communication cores |
2024-04-18 20:33:04 |
librecell-common |
0.0.16 |
Common utility functions for LibreCell suite. |
2024-04-14 20:01:41 |
slvcodec |
0.4.18 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2024-02-27 18:25:50 |
anyv-registers |
0.1.0 |
A template-based hardware register bank generator |
2024-02-25 13:44:24 |
magia-hdl |
0.5.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-02-20 20:35:45 |
magia-ip |
0.0.1 |
IP libraries designed with Magia |
2024-02-18 21:21:15 |
lclayout |
0.0.18 |
CMOS standard-cell layout generator. |
2024-01-28 21:50:19 |
asic |
0.2.5 |
Download and format ASIC files |
2024-01-26 03:13:11 |
syn-magia |
0.3.0 |
Magia generates Synthesizable SystemVerilog in pythonic syntax |
2024-01-06 20:57:03 |
litex |
2023.12 |
Python SoC/Core builder for building FPGA based systems. |
2023-12-28 20:49:13 |
picotalk |
0.0.24 |
Simple voice call tool. |
2023-12-15 14:00:45 |
peakrdl |
1.1.0 |
Command-line tool for control/status register automation and code generation. |
2023-10-26 04:34:44 |
litedram |
2023.8 |
Small footprint and configurable DRAM core |
2023-09-17 22:02:31 |
xeda |
0.2.5 |
Cross EDA Abstraction and Automation |
2023-07-26 17:38:36 |
liteeth |
2022.12 |
Small footprint and configurable Ethernet core |
2023-04-11 18:09:25 |
litepcie |
2022.12 |
Small footprint and configurable PCIe core |
2023-04-07 23:10:42 |
ipyxact |
0.3.2 |
Python IP-Xact handling library |
2022-06-15 20:30:00 |