Name | Version | Summary | date |
BICSdifftest |
1.0.1 |
Differential Testing Framework for Verilog Hardware Verification |
2025-08-24 09:24:01 |
vsc-dm |
0.0.1.17182848390 |
Core Verification Stimulus and Coverage library |
2025-08-24 02:12:06 |
jtag-axi |
0.1.5 |
JTAG to AXI bridge python I/F |
2025-08-20 09:29:31 |
mooreio-client |
2.1.9 |
CLI tool to automate EDA tasks for ASICs, FPGAs, and UVM IP. |
2025-08-19 02:13:13 |
peakrdl-viz |
1.0.2 |
Generate visualization code for MakerChip VIZ framework. |
2025-08-13 18:29:39 |
pytcl-eda |
0.3.0 |
PyTCL allows control EDA tools directly from Python that use TCL |
2025-08-11 07:27:29 |
pyslang |
9.0.0 |
Python bindings for slang, a library for compiling SystemVerilog |
2025-07-31 12:18:48 |
hdltree |
0.5.2 |
Pure Python HDL parser, plus symbol generator and sphinx domain |
2025-07-13 23:19:51 |
zuspec-be-py |
0.0.1.14003524440 |
Co-specification of hardware, software, design, and test behavior |
2025-03-22 00:56:45 |
vsc-solvers |
0.0.1.13937968163 |
Core Verification Stimulus and Coverage library |
2025-03-19 03:09:55 |
pyhdl-if |
0.0.2.13849311719 |
Python interface for HDL programming interfaces |
2025-03-14 03:34:25 |
ichier |
0.2.4 |
Integrated Circuit Hierarchy |
2025-02-23 11:23:12 |
zuspec-cli |
0.0.1.13321310739 |
Co-specification of hardware, software, design, and test behavior |
2025-02-14 02:34:16 |
tsfpga |
13.1.1 |
A flexible and scalable development platform for modern FPGA projects |
2025-02-12 13:43:08 |
zuspec-sv |
0.0.9 |
Core ARL data model library |
2025-02-12 03:02:40 |
zuspec-be-sw |
0.0.9 |
Backend library to generate software output |
2025-02-12 02:45:03 |
zuspec-arl-eval |
0.0.9 |
Core ARL data model library |
2025-02-12 02:44:37 |
zuspec-arl-dm |
0.0.9 |
Core ARL data model library |
2025-02-12 02:37:06 |
ivpm |
1.1.4.13232874283 |
IVPM (IP and Verification Package Manager) is a project-internal package manager. |
2025-02-10 03:20:24 |
uvm-python |
0.4.0 |
uvm-python UVM implementation in Python on top of cocotb |
2025-02-09 13:12:28 |