PyDigger - unearthing stuff about Python


NameVersionSummarydate
pyrilog 0.2.4 A Python-based SystemVerilog code generator using context managers 2025-09-09 18:02:31
ipxact2systemverilog 1.0.27 Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description 2025-08-28 18:11:39
jtag-axi 0.1.5 JTAG to AXI bridge python I/F 2025-08-20 09:29:31
peakrdl-viz 1.0.2 Generate visualization code for MakerChip VIZ framework. 2025-08-13 18:29:39
pytcl-eda 0.3.0 PyTCL allows control EDA tools directly from Python that use TCL 2025-08-11 07:27:29
pyslang 9.0.0 Python bindings for slang, a library for compiling SystemVerilog 2025-07-31 12:18:48
tree-sitter-systemverilog 0.2.1 SystemVerilog 1800-2023 Parser 2025-07-20 16:00:30
hdltree 0.5.2 Pure Python HDL parser, plus symbol generator and sphinx domain 2025-07-13 23:19:51
zuspec-be-py 0.0.1.14003524440 Co-specification of hardware, software, design, and test behavior 2025-03-22 00:56:45
zuspec-cli 0.0.1.13321310739 Co-specification of hardware, software, design, and test behavior 2025-02-14 02:34:16
tsfpga 13.1.1 A flexible and scalable development platform for modern FPGA projects 2025-02-12 13:43:08
uvm-python 0.4.0 uvm-python UVM implementation in Python on top of cocotb 2025-02-09 13:12:28
cocotbext-ahb 0.4.9 CocotbExt AHB Bus VIP 2025-01-25 18:58:04
peakrdl-regblock 0.23.0 Compile SystemRDL into a SystemVerilog control/status register (CSR) block 2024-12-20 06:06:20
peakrdl 1.2.3 Toolchain for control/status register automation and code generation. 2024-12-17 06:42:29
peakrdl-cli 1.2.3 Command-line tool for control/status register automation and code generation. 2024-12-17 06:41:36
cocotbext-waves 0.1.9 CocotbExt Wavedrom diagram generator 2024-11-01 20:03:31
svut 1.10.0 SystemVerilog Unit Test (SVUT) 2024-10-21 19:42:05
peakrdl-docx 0.4.7 Compile SystemRDL definition into a Docx (MsWord) document 2024-09-19 08:54:40
forastero 1.0 cocotb verification framework with the batteries included 2024-09-11 10:59:14
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