| Name | Version | Summary | date |
| tsfpga |
13.0.0 |
A flexible and scalable development platform for modern FPGA projects |
2024-10-14 06:43:29 |
| zuspec-be-sw |
0.0.1.11227251434 |
Backend library to generate software output |
2024-10-08 02:09:20 |
| jtag-axi |
0.1.4 |
JTAG to AXI bridge python I/F |
2024-10-07 19:03:51 |
| leap-backend |
0.1.0 |
The backend of the LEAP framework |
2024-10-05 07:30:54 |
| fusesoc |
2.4 |
Award-winnning package manager and build abstraction tool for HDL code |
2024-10-02 17:49:41 |
| cocotb-vivado |
0.0.4 |
Limited cocotb/Python interface for Xilinx Vivado Simulator |
2024-10-01 09:56:57 |
| pyucis |
0.1.4.11087239919 |
PyUCIS provides a Python API for manipulating UCIS coverage data. |
2024-09-28 21:47:24 |
| platformio |
6.1.16 |
Your Gateway to Embedded Software Development Excellence. Unlock the true potential of embedded software development with PlatformIO's collaborative ecosystem, embracing declarative principles, test-driven methodologies, and modern toolchains for unrivaled success. |
2024-09-26 10:32:34 |
| leap-frontend |
0.1.2 |
The frontend of the LEAP framework |
2024-09-23 04:47:51 |
| peakrdl-docx |
0.4.7 |
Compile SystemRDL definition into a Docx (MsWord) document |
2024-09-19 08:54:40 |
| zuspec-cli |
0.0.1.10874629242 |
Co-specification of hardware, software, design, and test behavior |
2024-09-15 22:04:06 |
| forastero |
1.0 |
cocotb verification framework with the batteries included |
2024-09-11 10:59:14 |
| vsc-solvers |
0.0.1.10703256703 |
Core Verification Stimulus and Coverage library |
2024-09-04 14:06:07 |
| zuspec-be-py |
0.0.1.10703132040 |
Co-specification of hardware, software, design, and test behavior |
2024-09-04 13:56:50 |
| jitcc |
0.0.1 |
Supports compiling and running C code on the fly |
2024-07-27 20:33:43 |
| rtlpy |
1.1.0 |
A Library of Python Utilities for RTL Design |
2024-06-12 16:54:41 |
| super-ide |
1.5.1 |
A professional Cross-platform IDE. Cross-platform IDE and Unified Debugger. Static Code Analyzer and Remote Unit Testing. Multi-platform and Multi-architecture Build System. Firmware File Explorer and Memory Inspection. IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbedOS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V, STMicroelectronics (STM8/STM32), Teensy |
2024-06-06 05:30:27 |
| mio-cli |
1.3.8 |
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA/ASIC projects. |
2024-05-17 12:13:59 |
| pyhdl-call-if |
0.0.1.8682446142 |
Python interface for HDL programming interfaces |
2024-04-15 02:48:41 |
| pyhdl-tlm-if |
0.0.1 |
Python interface for HDL programming interfaces |
2024-04-13 19:18:52 |