PyDigger - unearthing stuff about Python


NameVersionSummarydate
ichier 0.2.4 Integrated Circuit Hierarchy 2025-02-23 11:23:12
zuspec-cli 0.0.1.13321310739 Co-specification of hardware, software, design, and test behavior 2025-02-14 02:34:16
tsfpga 13.1.1 A flexible and scalable development platform for modern FPGA projects 2025-02-12 13:43:08
zuspec-sv 0.0.9 Core ARL data model library 2025-02-12 03:02:40
zuspec-be-sw 0.0.9 Backend library to generate software output 2025-02-12 02:45:03
zuspec-arl-eval 0.0.9 Core ARL data model library 2025-02-12 02:44:37
zuspec-arl-dm 0.0.9 Core ARL data model library 2025-02-12 02:37:06
uvm-python 0.4.0 uvm-python UVM implementation in Python on top of cocotb 2025-02-09 13:12:28
pytest-fv 0.0.1.13065020602 pytest extensions to support running functional-verification jobs 2025-01-31 02:09:45
zuspec-dataclasses 0.0.1.13064594382 Front-end for capturing Action Relation Level models using dataclasses 2025-01-31 01:29:39
cocotbext-ahb 0.4.9 CocotbExt AHB Bus VIP 2025-01-25 18:58:04
pyvsc-dataclasses 0.0.1.12773179088 Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses 2025-01-14 17:33:41
peakrdl-regblock 0.23.0 Compile SystemRDL into a SystemVerilog control/status register (CSR) block 2024-12-20 06:06:20
peakrdl 1.2.3 Toolchain for control/status register automation and code generation. 2024-12-17 06:42:29
peakrdl-cli 1.2.3 Command-line tool for control/status register automation and code generation. 2024-12-17 06:41:36
verilog-pad-analyzer 0.0.7 VerilogPADAnalyzer is a Python application designed to analyze and report the 2024-11-21 07:02:39
edalize 0.6.0 Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface 2024-11-13 20:05:24
tree-sitter-verilog 1.0.3 Verilog grammar for tree-sitter 2024-11-10 23:35:32
cocotbext-waves 0.1.9 CocotbExt Wavedrom diagram generator 2024-11-01 20:03:31
leap-backend 0.1.0 The backend of the LEAP framework 2024-10-05 07:30:54
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