| Name | Version | Summary | date |
| peakrdl-regblock |
0.23.0 |
Compile SystemRDL into a SystemVerilog control/status register (CSR) block |
2024-12-20 06:06:20 |
| systemrdl-compiler |
1.28.0 |
Parse and elaborate front-end for SystemRDL 2.0 |
2024-12-18 06:42:49 |
| peakrdl |
1.2.3 |
Toolchain for control/status register automation and code generation. |
2024-12-17 06:42:29 |
| peakrdl-cli |
1.2.3 |
Command-line tool for control/status register automation and code generation. |
2024-12-17 06:41:36 |
| hdl-registers |
6.2.0 |
An open-source HDL register interface code generator fast enough to run in real time |
2024-12-05 08:06:27 |
| slvcodec |
0.4.19 |
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python. |
2024-11-27 23:13:31 |
| enerbitdso |
0.1.18 |
enerBit DSO (Distribution System Operator) API client |
2024-11-20 13:59:57 |
| fusesoc |
2.4 |
Award-winnning package manager and build abstraction tool for HDL code |
2024-10-02 17:49:41 |
| peakrdl-docx |
0.4.7 |
Compile SystemRDL definition into a Docx (MsWord) document |
2024-09-19 08:54:40 |
| pywhatsminer |
0.2.2 |
Unofficial Python based Api-Client (Wrapper) for MicroBT Whatsminer ASIC`s |
2024-06-29 13:04:33 |
| magia-flow |
0.2.0 |
Design flow integration and automation with Magia |
2024-05-11 21:01:26 |
| lctime |
0.0.24 |
CMOS standard-cell characterization kit. |
2024-04-15 19:48:00 |
| librecell |
0.0.23 |
DEPRECATED - use `lctime` and `lclayout` packages - CMOS layout generator and characterization. |
2024-04-14 20:31:06 |
| librecell-layout |
0.0.23 |
DEPRECATED - use `lclayout` package instead - CMOS standard-cell layout generator. |
2024-04-14 20:28:43 |
| librecell-lib |
0.0.23 |
DEPRECATED - use `lctime` - CMOS standard-cell characterization kit. |
2024-04-14 20:28:09 |