| Name | Version | Summary | date |
| pyipcore |
0.4.23 |
(PyQt5 based) Create "Ipcore" from verilog(Need iverilog). Provide "Param Value" and "Port Control" function. This kind of IpCore is not safe, only for convenience |
2024-09-28 17:15:13 |
| svut |
1.9.2 |
SystemVerilog Unit Test (SVUT) |
2024-09-23 18:16:52 |
| sandpiper-saas |
1.1.0 |
Sandpiper SaaS |
2024-08-26 21:51:46 |
| mavsec |
0.0.1b2 |
A tool for the creation of JasperGold SVP principle tcl files. |
2024-03-27 22:48:13 |
| peakrdl-sv |
0.0.1 |
A SystemRDL exporter for SystemVerilog |
2024-03-07 11:54:22 |
| anyv-registers |
0.1.0 |
A template-based hardware register bank generator |
2024-02-25 13:44:24 |
| cocotb-vivado |
0.0.3 |
Limited cocotb/Python interface for Xilinx Vivado Simulator |
2024-02-12 10:28:27 |
| wal-lang |
0.8.0 |
Wal - Wavefile Analysis Language |
2024-01-29 17:06:21 |
| pyverilator-mm |
0.7.6 |
Python interface to Verilator models |
2024-01-21 11:25:40 |
| hdlConvertor-binary |
2.3 |
VHDL and System Verilog parser written in c++ |
2024-01-06 00:37:35 |
| sverilogpy |
0.0.0a2 |
A python System Verilog Parser and AST |
2024-01-03 16:47:25 |
| edalize |
0.5.4 |
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common interface |
2023-12-11 11:49:52 |
| zuspec |
0.0.1.6885112054 |
Co-specification of hardware, software, design, and test behavior |
2023-11-16 01:40:00 |
| zuspec-dataclasses |
0.0.1.6741044156 |
Front-end for capturing Action Relation Level models using dataclasses |
2023-11-03 03:50:05 |
| peakrdl |
1.1.0 |
Command-line tool for control/status register automation and code generation. |
2023-10-26 04:34:44 |
| hdlConvertorAst |
1.2 |
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities |
2023-10-23 13:53:41 |
| crcgen |
2.6 |
CRC algorithm HDL code generator (VHDL, Verilog, MyHDL) |
2023-10-13 20:56:15 |
| sphinxcontrib-hdl-diagrams |
0.0.post160 |
Generate diagrams from HDL in Sphinx. |
2023-09-21 05:39:48 |
| aide-core |
1.0.1000 |
A professional collaborative platform for embedded development. Cross-platform IDE and Unified Debugger. Static Code Analyzer and Remote Unit Testing. Multi-platform and Multi-architecture Build System. Firmware File Explorer and Memory Inspection. IoT, Arduino, CMSIS, ESP-IDF, FreeRTOS, libOpenCM3, mbedOS, Pulp OS, SPL, STM32Cube, Zephyr RTOS, ARM, AVR, Espressif (ESP8266/ESP32), FPGA, MCS-51 (8051), MSP430, Nordic (nRF51/nRF52), NXP i.MX RT, PIC32, RISC-V, STMicroelectronics (STM8/STM32), Teensy |
2023-08-29 14:17:47 |
| pySVModel |
0.4.1 |
An abstract SystemVerilog language model (incl. Verilog). |
2023-08-15 22:19:34 |